prof.dr. R.B. Staszewski

Professor
Electronics Research Laboratory (ELCA), Department of Microelectronics

Expertise: Large system-on-chip (SoC) designs for wireless applications; analog, RF, mixed-signal and digital designs; Digital RF

Themes: XG - Next Generation Sensing and Communication

Biography

Dr. Robert Bogdan Staszewski is an IEEE Fellow. He received the B.S.E.E. (summa cum laude), M.S.E.E. and Ph.D. degrees from the University of Texas at Dallas in 1991, 1992 and 2002, respectively. From 1991 to 1995 he was with Alcatel Network Systems in Richardson, Texas, USA, working on Sonnet cross-connect systems for fiber optics communications. He joined Texas Instruments in Dallas, Texas, USA, in 1995 where he was elected Distinguished Member of Technical Staff (2% of the technical population). Between 1995 and 1999, he had been engaged in advanced CMOS read channel development for hard disk drives. In 1999 he co-started a Digital RF Processor (DRP) group within Texas Instruments with a mission to invent new digitally-intensive approaches to traditional RF functions for integrated radios in deep-submicron CMOS processes. Dr. Staszewski was appointed a CTO of the DRP group between 2007 and 2009.

His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers. He has co-authored two books, four book chapters, 130 journal and conference publications, and holds 100 issued 50 pending US patents. Since July 2009 he is Associate Professor at Delft University of Technology in the Netherlands, and he was appointed as 'Antony van Leeuwenhoek' Full Professor in 2013.

Digitally Dominant Analog Blocks for Ultra-Low-Power Wireless Sensor Network

All-digital phase-locked loops, inductor/capacitor-based DC-DC switching converters

Projects history

Time-Domain RF and Analog Signal Processing

  1. Cryo-CMOS Circuits and Systems for Quantum Computing Applications
    Bishnu Patra; Rosario M. Incandela; Jeroen P. G. van Dijk; Harald A. R. Homulle; Lin Song; Mina Shahmohammadi; Robert B. Staszewski; Andrei Vladimirescu; Masoud Babaie; Fabio Sebastiano; Edoardo Charbon;
    IEEE Journal of Solid-State Circuits,
    Volume 53, Issue 1, pp. 1-13, Jan 2018. DOI: 10.1109/JSSC.2017.2737549
    Keywords: ... CMOS technology;Cryogenics;Oscillators;Process control;Quantum computing;Temperature;CMOS characterization;Class-F oscillator;cryo-CMOS;low-noise amplifier (LNA);noise canceling;phase noise (PN);quantum bit (qubit);quantum computing;qubit control;single-photon avalanche diode (SPAD)..

    Abstract: ...
    A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3 digitally controlled oscillator required to manipulate the state of qubits.

  2. Cryo-CMOS Circuits and Systems for Quantum Computing Applications
    B. Patra; R. M. Incandela; J. P. G. van Dijk; H. A. R. Homulle; L. Song; M. Shahmohammadi; R. B. Staszewski; A. Vladimirescu; M. Babaie; F. Sebastiano; E. Charbon;
    IEEE Journal of Solid-State Circuits,
    Volume 53, Issue 1, pp. 309-321, Jan 2018. DOI: 10.1109/JSSC.2017.2737549
    Keywords: ... CMOS technology;Cryogenics;Oscillators;Process control;Quantum computing;Temperature;CMOS characterization;Class-F oscillator;cryo-CMOS;low-noise amplifier (LNA);noise canceling;phase noise (PN);quantum bit (qubit);quantum computing;qubit control;single-photon avalanche diode (SPAD).

  3. A 0.45V sub-mW all-digital PLL in 16nm FinFET for Bluetooth Low-Energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference
    M.-S. Yuan, C.-C. Li, C.-C. Liao, Y.-T. Lin, C.-H. Chang,; R. B. Staszewski;
    In Proc. of IEEE Solid-State Circuits Conf. (ISSCC,
    2018.

  4. An ultracompact 9.4–14.8-GHz transformer-based fractional-N all-digital PLL in 40-nm CMOS
    A. R. Ximenes, G. Vlachogiannakis,; R. B. Staszewski;
    IEEE Trans. on Microwave Theory and Techniques (TMTT),
    Volume 65, Issue 11, pp. 4241–4254, 2017. DOI: 10.1109/TMTT.2017.2687901

  5. A 3.5–6.8-GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ-TDC for low in-band phase noise
    Y. Wu, M. Shahmohammadi, Y. Chen, P. Lu,; R. B. Staszewski;
    IEEE Journal of Solid-State Circuits (JSSC),
    Volume 52, Issue 7, pp. 1885–1903, July 2017. DOI: 10.1109/JSSC.2017.2682841

  6. Tuning range extension of a transformer-based oscillator through common-mode Colpitts resonance
    M. Shahmohammadi; M. Babaie; R. B. Staszewski;
    IEEE Trans. on Circuits and Systems I (TCAS-I),,
    Volume 64, Issue 4, pp. 836–846, April 2017. DOI: 10.1109/TCSI.2016.2625199

  7. A Bluetooth low-energy transceiver with 3.7-mW all-digital transmitter, 2.75-mW high-IF discrete-time receiver, and TX/RX switchable on-chip matching network
    F.-W. Kuo, S. Binsfeld Ferreira, H.-N. R. Chen, L.-C. Cho, C.-P. Jou, F.-L. Hsueh, I. Madadi, M. Tohidian, M. Shahmohammadi, M. Babaie,; R. B. Staszewski;
    IEEE Journal of Solid-State Circuits (JSSC),,
    Volume 52, Issue 4, pp. 1144–1162, April 2017. DOI: 10.1109/JSSC.2017.2654322

  8. A fully integrated discrete-time superheterodyne receiver
    M. Tohidian, I. Madadi,; R. B. Staszewski;
    IEEE Trans. on VLSI Systems (TVLSI,
    Volume 25, Issue 2, pp. 635–647, Feb 2017. DOI: DOI: 10.1109/TVLSI.2016.2598857

  9. Cryo-CMOS circuits and systems for scalable quantum computing
    Edoardo Charbon; Fabio Sebastiano; Masoud Babaie; Andrei Vladimirescu; Mina Shahmohammadi; R. B. Staszewski; Harald A. R. Homulle; Bishnu Patra; Jeroen P. G. van Dijk; Rosario M. Incandela; Lin Song; Bahador Valizadehpasha;
    In 2017 IEEE International Solid-State Circuits Conference (ISSCC),
    pp. 264-265, Feb 2017. DOI: 10.1109/ISSCC.2017.7870362
    Keywords: ... CMOS integrated circuits;logic circuits;quantum computing;cryo-CMOS circuits;error-correcting loop;quantum algorithm;quantum bits arrays;quantum coherence loss;qubit states;room-temperature controller;scalable quantum computing;state-of-the-art quantum processors;unprecedented computation power;Cryogenics;Oscillators;Program processors;Quantum computing;Semiconductor device modeling;Substrates;Temperature sensors.

    Abstract: ...
    In Paper 15.5, Delft University of Technology, EPFL, and Intel present building blocks for a scalable CMOS interface to solid-state quantum processors with a projected efficiency of 200�W/qubit. The circuits include an analog noise-canceled 1.2GHz LNA with 28dB gain, a 6.2GHz class-F local oscillator with better than �145dBc/Hz phase noise at 10MHz offset, a 12µm SPAD with 0.1Hz dark count rate at 2V excess bias, and digital logic, all designed using ad hoc deep-cryogenic models.

  10. A 350-mV 2.4GHz Quadrature Oscillator with Nearly Instantaneous Start-Up Using Series LC Tanks
    Y. Chen, M. Babaie,; R. B. Staszewski;
    In Proc. of IEEE Asian Solid-State Circuits Conf. (A-SSCC,
    IEEE, pp. 105-108, Nov 2017. DOI: 10.1109/ASSCC.2017.8240227

  11. A 15-uW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS
    P. Chen, F. Zhang, Z. Zong, H. Zheng, T. Siriburanon,; R. B. Staszewski;
    In Proc. of IEEE Asian Solid-State Circuits Conf. (A-SSCC,
    pp. 93-96, Nov 2017. DOI: 10.1109/ASSCC.2017.8240224

  12. A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS
    F.-W. Kuo, S. Pourmousavian, T. Siriburanon, R. Chen, L.-C. Cho, C.-P. Jou, F.-L. Hsueh,; R. B. Staszewski;
    In Proc. of IEEE Symp. on VLSI Circuits (VLSI,
    June 2017. DOI: 10.23919/VLSIC.2017.8008472

  13. A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner
    Y. Hu; T. Siriburanon; R. B. Staszewski;
    In ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference,
    pp. 87-90, Sept 2017. DOI: 10.1109/ESSCIRC.2017.8094532
    Keywords: ... CMOS integrated circuits;MMIC oscillators;capacitors;field effect MIMIC;flicker noise;phase noise;voltage-controlled oscillators;class-F operation;common-mode current return path;embedded decoupling capacitor;flicker noise;flicker phase-noise;frequency 10.0 GHz;frequency 120.0 kHz;frequency 27.3 GHz;frequency 27.3 GHz to 31.2 GHz;frequency 30.0 GHz;frequency generation;harmonic extraction;high quality factor;mmW frequency generation stage;noise figure -184.0 dB;phase noise;second-harmonic tank resonance;size 28.0 nm;third-harmonic boosting;waveform shaping;1f noise;Capacitors;Harmonic analysis;Inductance;Oscillators;Power harmonic filters;Resonant frequency;30GHz;5G Communication;low flicker noise corner;low phase noise;oscillator.

  14. Oscillator-based ADCs: An exploration of time-mode analog-to-digital conversion
    V. Nguyen; F. Schembari; R. B. Staszewski;
    In 2017 3rd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP),
    pp. 1-6, May 2017. DOI: 10.1109/EBCCSP.2017.8022829
    Keywords: ... analogue-digital conversion;injection locked oscillators;integrated circuit modelling;low-power electronics;voltage-controlled oscillators;VCO-based analog-to-digital converter;oscillator-based ADC;self-injection-locked ring-oscillator;time-mode oscillator-based analog-to-digital conversion;voltage 0.2 V;voltage-to-frequency characteristic;Delays;Frequency conversion;Topology;Transistors;Tuning;Voltage-controlled oscillators;Analog-to-digital converter (ADC);Internet-of-Things;Verilog-A modelling;time-domain ADC;ultra-low power;ultra-low voltage;voltage-controlled oscillator (VCO).

  15. A 770pJ/b 0.85V 0.3mm2 DCO-based phase-tracking RX featuring direct demodulation and data-aided carrier tracking for IoT applications
    Y. H. Liu; V. K. Purushothaman; C. Lu; J. Dijkhuis; R. B. Staszewski; C. Bachmann; K. Philips;
    In 2017 IEEE International Solid-State Circuits Conference (ISSCC),
    pp. 408-409, Feb 2017. DOI: 10.1109/ISSCC.2017.7870434

  16. A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications
    C. C. Li; M. S. Yuan; C. H. Chang; Y. T. Lin; C. C. Liao; K. Hsieh; M. Chen; R. B. Staszewski;
    In 2017 IEEE International Solid-State Circuits Conference (ISSCC),
    pp. 332-333, Feb 2017. DOI: 10.1109/ISSCC.2017.7870396
    Keywords: ... DC-DC power converters;FinFETs;Logic gates;Oscillators;Switches;Topology;Voltage control.

  17. 15.5 Cryo-CMOS circuits and systems for scalable quantum computing
    E. Charbon; F. Sebastiano; M. Babaie; A. Vladimirescu; M. Shahmohammadi; R. B. Staszewski; H. A. R. Homulle; B. Patra; J. P. G. van Dijk; R. M. Incandela; L. Song; B. Valizadehpasha;
    In 2017 IEEE International Solid-State Circuits Conference (ISSCC),
    pp. 264-265, Feb 2017. DOI: 10.1109/ISSCC.2017.7870362
    Keywords: ... Cryogenics;Oscillators;Program processors;Quantum computing;Semiconductor device modeling;Substrates;Temperature sensors.

  18. An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS
    Y. H. Liu; J. van den Heuvel; T. Kuramochi; B. Busze; P. Mateman; V. K. Chillara; B. Wang; R. B. Staszewski; K. Philips;
    IEEE Transactions on Circuits and Systems I: Regular Papers,
    Volume PP, Issue 99, pp. 1-12, 2016.

  19. A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators
    M. Shahmohammadi; M. Babaie; R. B. Staszewski;
    IEEE Journal of Solid-State Circuits,
    Volume 51, Issue 11, pp. 2610-2624, Nov 2016. DOI: 10.1109/JSSC.2016.2602214
    Keywords: ... 1/f noise;CMOS integrated circuits;LC circuits;flicker noise;harmonics suppression;interference suppression;phase noise;radiofrequency oscillators;1/f noise upconversion reduction technique;CMOS technology;class-D oscillators;class-F oscillators;common mode excitations;current harmonics;differential mode excitations;equivalent resistance;flicker noise upconversion;inductor based tanks;phase noise;tank current;transformer based tanks;voltage biased RF CMOS oscillators;Capacitors;Harmonic analysis;Oscillators;Radio frequency;Resistors;Resonant frequency;Transistors;Class-D oscillator;class-F oscillator;digitally controlled oscillator;flicker noise;flicker noise upconversion;impulse sensitivity function (ISF);phase noise (PN);voltage-biased RF oscillator.

  20. A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36\% System Efficiency at 3 dBm
    M. Babaie; F. W. Kuo; H. N. R. Chen; L. C. Cho; C. P. Jou; F. L. Hsueh; M. Shahmohammadi; R. B. Staszewski;
    IEEE Journal of Solid-State Circuits,
    Volume 51, Issue 7, pp. 1547-1565, July 2016. DOI: 10.1109/JSSC.2016.2551738
    Keywords: ... Bluetooth;CMOS digital integrated circuits;MOSFET circuits;constant current sources;digital phase locked loops;low-power electronics;oscillators;radio transmitters;radiofrequency integrated circuits;radiofrequency power amplifiers;1/f noise reduction;Bluetooth low-energy mode;CMOS transistors;all-digital PLL;class-E-F2 switching power amplifier;digitally controlled oscillator;direct DCO data modulation;efficiency 36 percent;energy-hungry RF circuits;fully integrated Bluetooth low-energy transmitter architecture;metal density;power 3.6 mW;power 5.5 mW;sampling rate reduction;size 28 nm;supply voltage reduction;switching current sources;threshold voltage;ultra-low power radios;CMOS integrated circuits;Inductors;Oscillators;Q-factor;Radio frequency;Radio transmitters;Switches;All-digital PLL;Bluetooth Low-Energy;Internet of Things (IoT);class-E/F 2 power amplifier;low-power transmitter;low-voltage oscillator;switching current-source oscillator.

  21. A Digitally Controlled Injection-Locked Oscillator With Fine Frequency Resolution
    I. Bashir; R. B. Staszewski; P. T. Balsara;
    IEEE Journal of Solid-State Circuits,
    Volume 51, Issue 6, pp. 1347-1360, June 2016. DOI: 10.1109/JSSC.2016.2539342
    Keywords: ... LC circuits;MMIC oscillators;circuit tuning;field effect MMIC;frequency modulation;injection locked oscillators;DCO step size;LC-tank;TSMC digital CMOS;amplitude manipulation;auxiliary loop;digitally controlled injection-locked RF oscillator;frequency 4 GHz;frequency modulation;injection strength;phase manipulation;size 40 nm;time-delayed resonating voltage;tuning range;Capacitors;Frequency modulation;Injection-locked oscillators;Tuning;All-digital PLL (ADPLL);digital phase rotator (DPR);digital-to-frequency converter (DFC);digitally controlled delay (DCD);digitally controlled oscillator (DCO);multi-stage noise Σ Δ (MASH);multi-stage noise ΣΔ (MASH).

  22. A 60 GHz Frequency Generator Based on a 20 GHz Oscillator and an Implicit Multiplier
    Z. Zong; M. Babaie; R. B. Staszewski;
    IEEE Journal of Solid-State Circuits,
    Volume 51, Issue 5, pp. 1261-1273, May 2016. DOI: 10.1109/JSSC.2016.2528997
    Keywords: ... CMOS digital integrated circuits;field effect MIMIC;frequency multipliers;millimetre wave frequency convertors;millimetre wave oscillators;phase noise;FoM;PN performance;digital CMOS process;extraction techniques;figure-of-merit;frequency 20 GHz;frequency 57.8 GHz;frequency 60 GHz;frequency generator;frequency tuning range;implicit multiplier;local oscillator signal;mm-wave frequency generation technique;phase detection;phase noise performance;phase-locked loop;power efficiency;size 40 nm;third-harmonic boosting techniques;Boosting;Frequency conversion;Harmonic analysis;Oscillators;Phase locked loops;Power demand;Resonant frequency;60 GHz;60 GHz;PLL;frequency divider;harmonic boosting;harmonic extraction;implicit multiplier;mm-wave;oscillator;phase noise (PN);transformer.

  23. Analysis and Design of a Multi-Core Oscillator for Ultra-Low Phase Noise
    S. A. R. Ahmadi-Mehr; M. Tohidian; R. B. Staszewski;
    IEEE Transactions on Circuits and Systems I: Regular Papers,
    Volume 63, Issue 4, pp. 529-539, April 2016. DOI: 10.1109/TCSI.2016.2529218
    Keywords: ... CMOS integrated circuits;LC circuits;MMIC oscillators;field effect MMIC;network analysis;network synthesis;phase noise;RF oscillator;current 39 mA to 59 mA;digital CMOS technology;dualcore LC-tank oscillator;frequency 4.07 GHz to 4.91 GHz;high swing class-C topology;multicore oscillator;phase noise reduction;ultralow phase noise;voltage 2.15 V;CMOS integrated circuits;Inductance;Inductors;Phase noise;Power demand;Topology;Basestation (BTS);LC-tank;class-C oscillator;coupled oscillators;figure of merit (FoM);phase noise.

  24. Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division
    S. A. R. Ahmadi Mehr; M. Tohidian; R. B. Staszewski;
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
    Volume 24, Issue 3, pp. 1071-1082, March 2016. DOI: 10.1109/TVLSI.2015.2436979
    Keywords: ... frequency dividers;system-on-chip;LC-tank oscillator;RF system on chips;digital fractional divider;frequency divider;frequency planning technique;high-swing class-C oscillator;integer harmonic frequency relationship;multichannel RF-SoC integration;phase rotator;Couplings;Frequency conversion;Frequency modulation;Harmonic analysis;Oscillators;Radio frequency;Substrates;Digital fractional divider;RF-SoC;digitally controlled oscillator (DCO);frequency pulling;injection locking;multi-core radio;system on chip (SoC);system on chip (SoC)..

  25. A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection
    I. Madadi; M. Tohidian; K. Cornelissens; P. Vandenameele; R. B. Staszewski;
    IEEE Journal of Solid-State Circuits,
    Volume 51, Issue 2, pp. 332-347, Feb 2016. DOI: 10.1109/JSSC.2015.2504414
    Keywords: ... CMOS integrated circuits;band-pass filters;superheterodyne receivers;surface acoustic wave devices;4G cellular applications;CMOS;IIP2 SAW-less superheterodyne receiver;blocker-resilient octal charge-sharing bandpass filter;cascaded harmonic rejection circuitry;multistage harmonic rejection;power 22 mW to 40 mW;size 28 nm;surface acoustic wave-less superheterodyne receiver;wideband noise-canceling low-noise transconductance amplifier;Band-pass filters;Calibration;Capacitors;Mixers;Radio frequency;Receivers;Surface acoustic waves;Bandpass filter (BPF);IIP2;charge-sharing;discrete-time;process-scalable;receiver;superheterodyne;surface acoustic wave (SAW)-less.

  26. A 5.9 GHz RFDAC-based outphasing power amplifier in 40-nm CMOS with 49.2% efficiency and 22.2 dBm power
    Z. Hu; L. C. N. de Vreede; M. S. Alavi; D. A. Calvillo-Cortes; R. B. Staszewski; S. He;
    In 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
    pp. 206-209, May 2016. DOI: 10.1109/RFIC.2016.7508287
    Keywords: ... CMOS integrated circuits;differential amplifiers;digital-analogue conversion;radiofrequency power amplifiers;CMOS;RFDAC-based outphasing power amplifier;ROPA drain;complementary metal oxide semiconductor;differential quasiload-insensitive class-E branch PA;digital amplitude control word;efficiency 49.2 percent;frequency 5.9 GHz;power back-off;radiofrequency digital-to-analog converter;segmentation technique;size 40 nm;word length 3 bit;Bandwidth;CMOS integrated circuits;Dynamic range;Loading;Modulation;Power generation;Switches;CMOS power amplifier;Chireix combiner;Class-E;Outphasing power amplifier;RFDAC.

  27. Exponential extended flash time-to-digital converter
    P. Chen; R. B. Staszewski;
    In 2016 Second International Conference on Event-based Control, Communication, and Signal Processing (EBCCSP),
    pp. 1-4, June 2016. DOI: 10.1109/EBCCSP.2016.7605281
    Keywords: ... calibration;digital phase locked loops;oscillators;power consumption;time-digital conversion;ADPLL;DCO;DTC;TDC gain calibration;all-digital phase locked loop;digital controlled oscillator;digital-to-time converter;exponential extended flash time-to-digital converter;ultralower power consumption characteristic;Calibration;Capacitance;Capacitors;Delays;Inverters;Load modeling;Loading;DLL;DTC-based ADPLL;TDC;exponential;two stages.

  28. A 0.5ps 1.4mW 50MS/s Nyquist bandwidth time amplifier based two-step flash- #x0394; #x03A3; time-to-digital converter
    Y. Wu; R. B. Staszewski;
    In 2016 Second International Conference on Event-based Control, Communication, and Signal Processing (EBCCSP),
    pp. 1-4, June 2016. DOI: 10.1109/EBCCSP.2016.7605282
    Keywords: ... CMOS digital integrated circuits;amplifiers;delta-sigma modulation;nanoelectronics;time-digital conversion;CMOS;Nyquist bandwidth time amplifier;current 1.3 mA;integrated TDC error;power 1.4 mW;shaped quantization noise;size 40 nm;time 0.5 ps;two-step flash-ΔΣ time-to-digital converter;voltage 1.1 V;Adders;Bandwidth;Calibration;Delays;Multi-stage noise shaping;Quantization (signal);Time-domain analysis;MASH;Noise shaping;TDC;error feedback;time amplifier;time domain register;time-interleaved;two-step.

  29. A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH Sigma-Delta TDC for low in-band phase noise
    Y. Wu; M. Shahmohammadi; Y. Chen; P. Lu; R. B. Staszewski;
    In ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference,
    pp. 209-212, Sept 2016. DOI: 10.1109/ESSCIRC.2016.7598279
    Keywords: ... delta-sigma modulation;digital phase locked loops;integrated circuit noise;jitter;oscillators;phase noise;time-digital conversion;ADPLL;DTC-assisted fractional-N all-digital PLL;MASH ΔΣ TDC;digital-to-time converter;frequency 1.73 GHz to 3.38 GHz;frequency 3.5 GHz to 6.8 GHz;integrated jitter;low-in-band phase noise;power 10.7 mW;size 40 nm;wide-tuning range DCO;wide-tuning range digitally-controlled oscillator;Delays;Frequency measurement;Jitter;Multi-stage noise shaping;Phase locked loops;Phase noise;Tuning;All digital PLL;BBPD;DCO;DTC;MASH;TDC;noise shaping;wide-bandwidth;wide-tuning range.

  30. A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter
    F. W. Kuo; S. B. Ferreira; M. Babaie; R. Chen; L. c. Cho; C. P. Jou; F. L. Hsueh; G. Huang; I. Madadi; M. Tohidian; R. B. Staszewski;
    In 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits),
    pp. 1-2, June 2016. DOI: 10.1109/VLSIC.2016.7573480
    Keywords: ... Bluetooth;Internet of Things;MOS integrated circuits;band-pass filters;oscillators;phase locked loops;radio transceivers;radio transmitters;1-pin direct antenna connection;Bluetooth LE;Bluetooth low-energy transceiver;CMOS;Internet-of-Things;IoT;MOS devices;TX/RX switchable on-chip matching network;The receiver;all-digital PLL;all-digital transmitter;discrete-time architecture;high-IF discrete-time receiver;integrated on-chip matching network;multirate charge-sharing bandpass filters;power 2.75 mW;power 3.6 mW;power consumption;size 28 nm;switched-current-source digitally controlled oscillator;transmitter;ultra-low-power transceiver;Band-pass filters;Capacitors;Gain;Power demand;Switches;System-on-chip;Transceivers.

  31. A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS
    Chao-Chieh Li; T. H. Tsai; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo; K. Hsieh; M. Chen; A. Ximenes; R. B. Staszewski;
    In 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits),
    pp. 1-2, June 2016. DOI: 10.1109/VLSIC.2016.7573551
    Keywords: ... CMOS integrated circuits;MOSFET circuits;digital phase locked loops;transformers;DCO;FinFET CMOS;LC-tank-based ADPLL;capacitor banks;fractional-N all-digital PLL;frequency 10.8 GHz to 19.3 GHz;frequency reference clock;inverter-based ring-oscillator PLL;magnetic coupling transformer;metastability-resolution scheme;size 10 nm;time 725 fs;Capacitors;Clocks;FinFETs;Jitter;Phase locked loops;Q-factor;Tuning.

  32. Fast Computing Framework for Convolutional Neural Networks
    M. Korytkowski; P. Staszewski; P. Woldan; R. Scherer;
    In 2016 IEEE International Conferences on Big Data and Cloud Computing (BDCloud), Social Computing and Networking (SocialCom), Sustainable Computing and Communications (SustainCom) (BDCloud-SocialCom-SustainCom),
    pp. 118-123, Oct 2016.

  33. A 38 GHz on-chip antenna in 28-nm CMOS using artificial magnetic conductor for 5G wireless systems
    M. K. Hedayati; A. Abdipour; R. S. Shirazi; M. John; M. J. Ammann; R. B. Staszewski;
    In 2016 Fourth International Conference on Millimeter-Wave and Terahertz Technologies (MMWaTT),
    pp. 29-32, Dec 2016. DOI: 10.1109/MMWaTT.2016.7869869
    Keywords: ... Antennas;Conductors;ISO Standards;Indexes;Radio frequency;System-on-chip;Wireless communication;28 nm CMOS;Fifth Generation (5G) wireless;artificial magnetic conductor (AMC);on-chip antenna (AoC).

  34. An Ultra-Low Phase Noise Class-F 2 CMOS Oscillator With 191 dBc/Hz FoM and Long-Term Reliability
    M. Babaie; R. B. Staszewski;
    IEEE Journal of Solid-State Circuits,
    Volume 50, Issue 3, pp. 679-692, March 2015.

  35. Design of Spur-Free \Sigma \Delta Frequency Tuning Interface for Digitally Controlled Oscillators
    J. Zhuang; K. Waheed; R. B. Staszewski;
    IEEE Transactions on Circuits and Systems II: Express Briefs,
    Volume 62, Issue 1, pp. 46-50, Jan 2015.

  36. A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm
    F. W. Kuo; M. Babaie; R. Chen; K. Yen; J. Y. Chien; L. Cho; F. Kuo; C. P. Jou; F. L. Hsueh; R. B. Staszewski;
    In ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC),
    pp. 356-359, Sept 2015.

  37. 25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators
    M. Shahmohammadi; M. Babaie; R. B. Staszewski;
    In 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers,
    pp. 1-3, Feb 2015.

  38. A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS
    I. Madadi; M. Tohidian; K. Cornelissens; P. Vandenameele; R. B. Staszewski;
    In 2015 Symposium on VLSI Circuits (VLSI Circuits),
    pp. C308-C309, June 2015.

  39. 14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S
    T. H. Tsai; M. S. Yuan; C. H. Chang; C. C. Liao; C. C. Li; R. B. Staszewski;
    In 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers,
    pp. 1-3, Feb 2015.

  40. A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS
    B. Wang; Y. H. Liu; P. Harpe; J. van den Heuvel; B. Liu; H. Gao; R. B. Staszewski;
    In 2015 IEEE International Symposium on Circuits and Systems (ISCAS),
    pp. 2289-2292, May 2015.

  41. An impedance sensor for MEMS adaptive antenna matching
    A. Tavakol; R. B. Staszewski;
    In 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
    pp. 379-382, May 2015.

  42. A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash- #x0394; #x03A3; time-to-digital converter for ADPLL
    Y. Wu; P. Lu; R. B. Staszewski;
    In 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
    pp. 95-98, May 2015.

  43. A 60 GHz 25% tuning range frequency generator with implicit divider based on third harmonic extraction with 182 dBc/Hz FoM
    Z. Zong; M. Babaie; R. B. Staszewski;
    In 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
    pp. 279-282, May 2015.

  44. A 0.5V 0.5mW switching current source oscillator
    M. Babaie; M. Shahmohammadi; R. B. Staszewski;
    In 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
    pp. 183-186, May 2015.

  45. A wideband 60 GHz class-E/F2 power amplifier in 40nm CMOS
    M. Babaie; R. B. Staszewski; L. Galatro; M. Spirito;
    In 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
    pp. 215-218, May 2015.

  46. Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter
    M. Tohidian; I. Madadi; R. B. Staszewski;
    IEEE Journal of Solid-State Circuits,
    Volume 49, Issue 11, pp. 2575-2587, Nov 2014.

  47. A Wideband 2 \times 13-bit All-Digital I/Q RF-DAC
    M. S. Alavi; R. B. Staszewski; L. C. N. de Vreede; J. R. Long;
    IEEE Transactions on Microwave Theory and Techniques,
    Volume 62, Issue 4, pp. 732-752, April 2014.

  48. A Low Phase Noise Oscillator Principled on Transformer-Coupled Hard Limiting
    A. Visweswaran; R. B. Staszewski; J. R. Long;
    IEEE Journal of Solid-State Circuits,
    Volume 49, Issue 2, pp. 373-383, Feb 2014.

  49. A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS
    W. Wu; R. B. Staszewski; J. R. Long;
    IEEE Journal of Solid-State Circuits,
    Volume 49, Issue 5, pp. 1081-1096, May 2014.

  50. 3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver
    M. Tohidian; I. Madadi; R. B. Staszewski;
    In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC),
    pp. 1-3, Feb 2014.

  51. A 2.4GHz class-D power amplifier with conduction angle calibration for #x2212;50dBc harmonic emissions
    A. Ba; V. K. Chillara; Y. H. Liu; H. Kato; K. Philips; R. B. Staszewski;
    In 2014 IEEE Radio Frequency Integrated Circuits Symposium,
    pp. 239-242, June 2014.

  52. 9.8 An 860 #x03BC;W 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications
    V. K. Chillara; Y. H. Liu; B. Wang; A. Ba; M. Vidojkovic; K. Philips; H. de Groot; R. B. Staszewski;
    In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC),
    pp. 172-173, Feb 2014.

  53. A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS
    Feng-Wei Kuo; R. Chen; K. Yen; Hsien-Yuan Liao; Chewn-Pu Jou; Fu-Lung Hsueh; M. Babaie; R. B. Staszewski;
    In 2014 Symposium on VLSI Circuits Digest of Technical Papers,
    pp. 1-2, June 2014.

  54. Design for test of a mm-Wave ADPLL-based transmitter
    W. Wu; R. B. Staszewski; J. R. Long;
    In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference,
    pp. 1-8, Sept 2014.

  55. A 1.2V 110-MHz-UGB differential class-AB amplifier in 65nm CMOS
    A. Visweswaran; J. R. Long; R. B. Staszewski;
    In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference,
    pp. 1-4, Sept 2014.

  56. A Class-F CMOS Oscillator
    M. Babaie; R. B. Staszewski;
    IEEE Journal of Solid-State Circuits,
    Volume 48, Issue 12, pp. 3120-3133, Dec 2013.

  57. High-Resolution Millimeter-Wave Digitally Controlled Oscillators With Reconfigurable Passive Resonators
    W. Wu; J. R. Long; R. B. Staszewski;
    IEEE Journal of Solid-State Circuits,
    Volume 48, Issue 11, pp. 2785-2794, Nov 2013.

  58. Dual-core high-swing class-C oscillator with ultra-low phase noise
    M. Tohidian; S. A. Reza Ahmadi Mehr; R. B. Staszewski;
    In 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
    pp. 243-246, June 2013.

  59. A mm-Wave FMCW radar transmitter based on a multirate ADPLL
    W. Wu; X. Bai; R. B. Staszewski; J. R. Long;
    In 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
    pp. 107-110, June 2013.

  60. Ultra-low phase noise 7.2 #x2013;8.7 Ghz clip-and-restore oscillator with 191 dBc/Hz FoM
    M. Babaie; A. Visweswaran; Z. He; R. B. Staszewski;
    In 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
    pp. 43-46, June 2013.

  61. A 65nm CMOS high-IF superheterodyne receiver with a High-Q complex BPF
    I. Madadi; M. Tohidian; R. B. Staszewski;
    In 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
    pp. 323-326, June 2013.

  62. A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS
    J. W. Lai; C. H. Wang; K. Kao; A. Lin; Y. H. Cho; L. Cho; M. H. Hung; X. Y. Shih; C. M. Lin; S. H. Yan; Y. H. Chung; P. C. P. Liang; G. K. Dehng; H. S. Li; G. Chien; R. B. Staszewski;
    In 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers,
    pp. 342-343, Feb 2013.

  63. A highly selective LNTA capable of large-signal handling for RF receiver front-ends
    M. Mehrpoo; R. B. Staszewski;
    In 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
    pp. 185-188, June 2013.

  64. A study of RF oscillator reliability in nanoscale CMOS
    M. Babaie; R. B. Staszewski;
    In 2013 European Conference on Circuit Theory and Design (ECCTD),
    pp. 1-4, Sept 2013.

  65. Third-harmonic injection technique applied to a 5.87-to-7.56GHz 65nm CMOS Class-F oscillator with 192dBc/Hz FOM
    M. Babaie; R. B. Staszewski;
    In 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers,
    pp. 348-349, Feb 2013.

  66. A 2mW 800MS/s 7th-order discrete-time IIR filter with 400kHz-to-30MHz BW and 100dB stop-band rejection in 65nm CMOS
    M. Tohidian; I. Madadi; R. B. Staszewski;
    In 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers,
    pp. 174-175, Feb 2013.

  67. A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS
    W. Wu; X. Bai; R. B. Staszewski; J. R. Long;
    In 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers,
    pp. 352-353, Feb 2013.

  68. Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL
    J. Zhuang; R. B. Staszewski;
    In 2013 European Conference on Circuit Theory and Design (ECCTD),
    pp. 1-4, Sept 2013.

  69. An FM demodulator operating across 2 #x2013;10GHz IF
    A. Visweswaran; J. R. Long; L. Galatro; M. Spirito; R. B. Staszewski;
    In 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
    pp. 213-216, June 2013.

  70. A 2 #x00D7;13-bit all-digital I/Q RF-DAC in 65-nm CMOS
    M. S. Alavi; G. Voicu; R. B. Staszewski; L. C. N. de Vreede; J. R. Long;
    In 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),
    pp. 167-170, June 2013.

  71. All-Digital RF I/Q Modulator
    M. S. Alavi; R. B. Staszewski; L. C. N. de Vreede; A. Visweswaran; J. R. Long;
    IEEE Transactions on Microwave Theory and Techniques,
    Volume 60, Issue 11, pp. 3513-3526, Nov 2012.

  72. Low Power Time-of-Flight 3D Imager System in Standard CMOS
    P. Kumar; E. Charbon; R.B. Staszewski;
    In Proc. IEEE Intl. Conference of Electronics, Circuits and Systems (ICECS),
    December 2012.
    document

  73. Low power time-of-flight 3D imager system in standard CMOS
    P. Kumar; E. Charbon; R. B. Staszewski; A. Borowski;
    In 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012),
    pp. 941-944, Dec 2012.

  74. High-resolution 60-GHz DCOs with reconfigurable distributed metal capacitors in passive resonators
    W. Wu; J. R. Long; R. B. Staszewski; J. J. Pekarik;
    In 2012 IEEE Radio Frequency Integrated Circuits Symposium,
    pp. 91-94, June 2012.

  75. Fine frequency tuning using injection-control in a 1.2V 65nm CMOS quadrature oscillator
    A. Visweswaran; R. B. Staszewski; J. R. Long; A. Akhnoukh;
    In 2012 IEEE Radio Frequency Integrated Circuits Symposium,
    pp. 293-296, June 2012.

  76. A clip-and-restore technique for phase desensitization in a 1.2V 65nm CMOS oscillator for cellular mobile and base stations
    A. Visweswaran; R. B. Staszewski; J. R. Long;
    In 2012 IEEE International Solid-State Circuits Conference,
    pp. 350-352, Feb 2012.

  77. A low-power all-digital PLL architecture based on phase prediction
    J. Zhuang; R. B. Staszewski;
    In 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012),
    pp. 797-800, Dec 2012.

  78. Is RF doomed to digitization? What shall RF circuit designers do?
    R. B. Staszewski; J. Rudell;
    In 2012 IEEE International Solid-State Circuits Conference,
    pp. 510-510, Feb 2012.

  79. A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter
    I. Bashir; R. B. Staszewski; O. Eliezer; B. Banerjee; P. T. Balsara;
    IEEE Journal of Solid-State Circuits,
    Volume 46, Issue 2, pp. 403-415, Feb 2011.

  80. Autonomous predistortion calibration of an RF power amplifier
    I. Bashir; R. B. Staszewski;
    In 2011 IEEE International Symposium of Circuits and Systems (ISCAS),
    pp. 205-208, May 2011.

  81. All-digital RF frequency modulation
    R. Bogdan Staszewski;
    In 2011 IEEE International Symposium of Circuits and Systems (ISCAS),
    pp. 426-429, May 2011.

  82. Dynamic bandwidth adjustment of an RF all-digital PLL
    R. B. Staszewski; I. Bashir; K. Waheed;
    In 2011 IEEE Radio Frequency Integrated Circuits Symposium,
    pp. 1-4, June 2011.

  83. Spur-free all-digital PLL in 65nm for mobile phones
    R. B. Staszewski; K. Waheed; S. Vemulapalli; F. Dulger; J. Wallberg; C. M. Hung; O. Eliezer;
    In 2011 IEEE International Solid-State Circuits Conference,
    pp. 52-54, Feb 2011.

  84. Cellular and wireless LAN transceivers: From systems to circuit design
    J. R. Long; H. Darabi; F. O. Eynde; B. Razavi; B. Staszewski;
    In 2011 IEEE International Solid-State Circuits Conference,
    pp. 524-524, Feb 2011.

  85. Orthogonal summing and power combining network in a 65-nm all-digital RF I/Q modulator
    M. S. Alavi; R. B. Staszewski; L. C. N. de Vreede; J. R. Long;
    In 2011 IEEE International Symposium on Radio-Frequency Integration Technology,
    pp. 21-24, Nov 2011.

  86. A 2-GHz digital I/Q modulator in 65-nm CMOS
    M. S. Alavi; A. Visweswaran; R. B. Staszewski; L. C. N. de Vreede; J. R. Long; A. Akhnoukh;
    In IEEE Asian Solid-State Circuits Conference 2011,
    pp. 277-280, Nov 2011.

BibTeX support

Last updated: 18 Sep 2017