dr.ir. Kumar

1. Comprehensive MPSP for Fast Optimal Control: Algorithm Development and Convergence Analysis
   Prem Kumar; Geethu Joseph; Chandra R. Murthy; Radhakant Padhi;
   Transactions of the Indian National Academy of Engineering,
   2024.

2. Vector Doppler imaging of small vessels using directionally filtered Power Doppler images
   B. Generowicz; L. Verhoef; F. Mastik; S. Dijkhuizen; N. van Dorp; J. Voorneveld; J. Bosch; K. Kumar; G. Leus; C. de Zeeuw; S. Koekkoek; P. Kruizinga;
   In 2020 IEEE International Ultrasonics Symposium (IUS),
   pp. 1-4, 2020. DOI: 10.1109/IUS46767.2020.9251356
   document

3. An Energy-Efficient BJT-Based Temperaure-to-Digital Converter with ±0.13 °C (3σ) Inaccuracy from -40 to 125°C
   R.K. Kumar; H. Jiang; K. A.A. Makinwa;
   In Proc. IEEE Asian Solid-State Circuits Conference (ASSCC),
   11 2019.

4. An Energy-Efficient BJT-Based Temperature-to-Digital Converter with ±0.13°C (3σ) Inaccuracy from -40 to 125°C
   Kumar, Rushil K.; Jiang, Hui; Makinwa, Kofi A. A.;
   In 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC),
   pp. 107-108, 2019. DOI: 10.1109/A-SSCC47793.2019.9056962

5. A sub-nW neuromorphic receptors for wide-range temporal patterns of post-synaptic responses in 65 nm CMOS
   X. You; A. Zjajo; S. Kumar; R. van Leuken;
   Analog Integrated Circuits and Signal Processing,
   2018. DOI: 10.1007/s10470-018-1276-4
   document

6. Advances in the electronics for cyclic voltammetry: the case of gas detection by using microfabricated electrodes
   Giorgio Pennazza; Marco Santonico; Luca Vollero; Alessandro Zompanti; Anna Sabatini; Nandeesh Kumar; Ivan Pini; William F Quiros Solano; Lina Sarro; Arnaldo D'Amico;
   Frontiers in Chemistry,
   Volume 6, pp. 327, 2018.
   document

7. Energy-Efficient Multipath Ring Network for Heterogeneous Clustered Neuronal Arrays
   A. Ardelean; A. Zjajo; S.S. Kumar; R. van Leuken;
   In IEEE Biomedical and Health Informatics (BHI),
   Las Vegas (USA), IEEE, pp. 190-193, March 2018. DOI: 10.1109/BHI.2018.8333401
   document

8. Multi-layer neuromorphic synapse for reconfigurable networks
   A. Zjajo; S. Kumar; R. van Leuken;
   In IEEE International Conference on Signal Processing,
   Beijing, China, pp. 997-1000, 2018.
   document

9. Uncertainty in noise-driven steady-state neuromorphic network for ECG data classificaiton
   A. Zjajo; J. Mes; E. Kolagasiogly; S. Kumar; R. van Leuken;
   In IEEE International Symposium on Computer Based Medical Systems,
   Karlstad, Sweden, pp. 434-435, 2018. ISSN 2372-9198. DOI: 10.1109/CBMS.2018.00082
   document

10. Fighting Dark Silicon: Toward Realizing Efficient Thermal-Aware 3-D Stacked Multiprocessors
    S.S. Kumar; A. Zjajo; T.G.R.M. van Leuken;
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
    Volume 25, Issue 4, pp. 1549-1562, 2017. ISSN 1063-8210. DOI: 10.1109/TVLSI.2016.2642587
    document

11. Immediate Neighborhood Temperature Adaptive Routing for Dynamically Throttled 3-D Networks-on-Chip
    S. S. Kumar; A. Zjajo; R. van Leuken;
    IEEE Transactions on Circuits and Systems II: Express Briefs,
    Volume 64, Issue 7, pp. 782-786, July 2017. ISSN 1549-7747. DOI: 10.1109/TCSII.2015.2503613
    document

12. Neuromorphic spike data classifier for reconfigurable brain-machine interface
    A. Zjajo; S. Kumar; R. van Leuken;
    In 2017 8th International IEEE/EMBS Conference on Neural Engineering (NER),
    pp. 150-153, May 2017. DOI: 10.1109/NER.2017.8008314
    document

13. Neuromorphic Self-Organizing Map Design for Classification of Bioelectric-Timescale Signals
    J. Mes; E. Stienstra; Xuefei You; S. Kumar; A. Zjajo; C. Galuzzi; R. van Leuken;
    In Int. Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XVII),
    July 2017.

14. Energy-Efficient Neuromorphic Receptors for Wide-Range Temporal Patterns of Post-Synaptic Responses
    Xuefei You; A. Zjajo; S. S. Kumar; R. van Leuken;
    In IEEE Nordic Circuits and Systems Conference (2017 NorCAS),
    Linkoping (Sweden), October 2017. DOI: 10.1109/NORCHIP.2017.8124951
    document

15. Exploration of the thermal design space in 3D integrated circuits
    S.S. Kumar; A. Zjajo; R. van Leuken;
    In Physical Design for 3D Integrated Circuits,
    CRC Press, 2016. ISBN: 978-1-4987-1037-4.

16. Immediate neighborhood temperature adaptive routing for 3D networks-on-chip
    S. Kumar; A. Zjajo; R. van Leuken;
    IEEE Transactions on Circuits and Systems-II: Express Briefs,
    2015. DOI: 10.1109/TCSII.2015.2503613
    document

17. Thermal Design of 3D Systems-on-Chip
    S. S. Kumar; A. Zjajo; R. van Leuken;
    In Physical Design for 3D Integrated Circuits,
    CRC Press, 2015. DOI: 978-87-929-8271-1
    document

18. Physical characterization of steady-state temperature profiles in three-dimensional integrated circuits
    S. Kumar; A. Zjajo; R. van Leuken;
    In IEEE International Symposium on Circuits and Systems,
    Lisbon, Portugal, pp. pp. 1969-1972, 2015.
    document

19. Ctherm: A integrated framework for thermal-functional co-simulation of systems-on-chip
    S. Kumar; A. Zjajo; R. van Leuken;
    In IEEE International Conference on Parallel, Distributed and Network-based Processing,
    Turku, Finland, pp. pp. 674-681, 2015.
    document

20. Thermal-Aware Design and Runtime Management of 3D Stacked Multiprocessors
    S.S. Kumar;
    PhD thesis, TU Delft, Fac. EEMCS, September 2015. ISBN 978-94-6186-513-7.
    document

21. Pronto: A Low Overhead Message Passing System for High Performance Many-Core Processors
    S.S. Kumar; Mitzi Tijin-A-Djie; T.G.R.M. van Leuken;
    International Journal of Networking and Computing,
    Volume 4, Issue 2, pp. 307-320, July 2014. ISSN 2185-2839.
    document

22. A System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3D MP-SoCs
    S.S. Kumar; A. Aggarwal; R. Jagtap; A. Zjajo; R. van Leuken;
    IEEE Tr. Very Large Scale Integration (VLSI) Systems,
    Volume 22, pp. 1606-1619, 2014.

23. Improving data cache performance using Persistence Selective Caching
    S.S. Kumar; T.G.R.M. van Leuken;
    In IEEE Int. Conf. Circuits and Systems (ISCAS),
    Melbourne, Australia, IEEE, pp. 1945-1948, June 2014. DOI: 10.1109/ISCAS.2014.6865542
    document

24. A System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3D MP-SoCs
    S. Kumar; A. Aggarwal; R. Jagtap; A. Zjajo; R. van Leuken;
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
    2013. in press.
    document

25. Cit: A GCC Plugin for the Analysis and Characterization of Data Dependencies in Parallel Programs
    S.S. Kumar; A. Chahar; R. van Leuken;
    In Int. Conf. Design of Circuits and Integrated Systems,
    San Sebastian (Spain), 2013.
    document

26. Low Overhead Message Passing for High Performance Many-Core Processors
    S.S. Kumar; M.E. Tjin-A-Djie; R. van Leuken;
    In Int. Symp. Computing and Networking,
    Matsuyama (Japan), 2013.
    document

27. Interconnect and Thermal Aware 3D Design Space Exploration
    S. Kumar; A. Aggarwal; R. Jagtap; A. Zjajo; R. van Leuken;
    In ICT.OPEN,
    Eindhoven, The Netherlands, 2013.
    document

28. Temperature Constrained Power Management Scheme for 3D MPSoC
    A. Aggarwal; S. Kumar; A. Zjajo; T.G.R.M. van Leuken;
    In Proceedings of SPI 2012,
    Sorrento, Italy, May 2012.
    document

29. A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICs
    R. Jagtap; S.S. Kumar; T.G.R.M. van Leuken;
    In 15th Euromicro Conference on Digital System Design,
    Cesme, Turkey, September 2012.

30. Low Power Time-of-Flight 3D Imager System in Standard CMOS
    P. Kumar; E. Charbon; R.B. Staszewski;
    In Proc. IEEE Intl. Conference of Electronics, Circuits and Systems (ICECS),
    December 2012.
    document

31. Low power time-of-flight 3D imager system in standard CMOS
    P. Kumar; E. Charbon; R. B. Staszewski; A. Borowski;
    In 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012),
    pp. 941-944, Dec 2012.

32. A 3D network-on-chip for stacked-die transactional chip multiprocessors using through silicon vias
    S.S. Kumar; T.G.R.M. van Leuken;
    In 2011 6th Int. Conf. on Design and Technology of Integrated Systems in Nanoscale Era (DTIS),
    Athens, Greece, IEEE, pp. 1-6, April 2011.
    document

33. TMFab--A Transactional Memory Fabric for Chip Multiprocessors
    S.S. Kumar; R. van Leuken;
    In Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP 2011),
    Grenoble, France, March 2011.

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