MSc Karmakar
Electronic Instrumentation (EI), Department of Microelectronics
Expertise: ADCs, High-Power Audio Amplifiers
Publications
Eland, Efraïm; Mehrotra, Shubham; Karmakar, Shoubhik; van Veldhoven, Robert; Makinwa, Kofi A. A.;
Harpe, Pieter; Baschirotto, Andrea; Makinwa, Kofi A.A. (Ed.);
Cham: Springer International Publishing, , pp. 179--201, 2023. DOI: 10.1007/978-3-031-28912-5_10
Abstract: ...
Zoom ADCs combine a coarse SAR ADC with a fine delta-sigma modulator ($\Delta$$\Sigma$M) to efficiently obtain high energy efficiency and high dynamic range. This makes them well suited for use in various instrumentation and audio applications. However, zoom ADCs also have drawbacks. The use of over-ranging in their fine modulators may limit SNDR, large out-of-band interferers may cause slope overload, and the quantization noise of their coarse ADC may leak into the baseband. This chapter presents an overview of recent advances in zoom ADCs that tackle these challenges while maintaining high energy efficiency. Prototypes designed in standard 0.16 $\mu$m technology achieve SNDRs over 100 dB in bandwidths ranging from 1 to 24 kHz while consuming only hundreds of $\mu$Ws.
Karmakar, Shoubhik; Berkhout, Marco; Makinwa, Kofi A. A.; Fan, Qinwen;
IEEE Journal of Solid-State Circuits,
Volume 57, Issue 12, pp. 3726-3735, 2022. DOI: 10.1109/JSSC.2022.3207386
Karmakar, Shoubhik; Berkhout, Marco; Makinwa, Kofi A. A.; Fan, Qinwen;
In 2022 IEEE International Solid-State Circuits Conference (ISSCC),
pp. 1-3, 2022. DOI: 10.1109/ISSCC42614.2022.9731736
Mehrotra, Shubham; Eland, Efraïm; Karmakar, Shoubhik; Liu, Angqi; Gönen, Burak; Bolatkale, Muhammed; Van Veldhoven, Robert; Makinwa, Kofi A.A.;
In ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC),
pp. 253-256, 2022. DOI: 10.1109/ESSCIRC55480.2022.9911295
E. Eland; S. Karmakar; B. Gönen; R. van Veldhoven; K. A. A. Makinwa;
IEEE Journal of Solid-State Circuits,
Volume 56, pp. 1207-1215, January 2021. DOI: 10.1109/JSSC.2020.3044896
Abstract: ...
This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta–sigma modulator ( ΔΣM ) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC’s quantization noise into the audio band. The prototype ADC occupies 0.27 mm 2 in a 0.16- μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW . It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB.
Zhang, Huajun; Karmakar, Shoubhik; Breems, Lucien J.; Sandifort, Quino; Berkhout, Marco; Makinwa, Kofi A. A.; Fan, Qinwen;
IEEE Journal of Solid-State Circuits,
Volume 56, Issue 4, pp. 1176-1185, 2021. DOI: 10.1109/JSSC.2020.3043815
Huajun Zhang; Shoubhik Karmakar; Lucien J. Breems; Quino Sandifort; Marco Berkhout; Kofi A. A. Makinwa; Qinwen Fan;
{IEEE} Journal of Solid-State Circuits,
Volume 56, Issue 4, pp. 1176--1185, April 2021. DOI: 10.1109/jssc.2020.3043815
document
Rooijers, Thije; Karmakar, Shoubhik; Kusuda, Yoshinori; Huijsing, Johan H.; Makinwa, Kofi A. A.;
IEEE Journal of Solid-State Circuits,
Volume 56, Issue 12, pp. 3583-3592, 2021. DOI: 10.1109/JSSC.2021.3107350
E. Eland; S. Karmakar; B. Gönen; R. van Veldhoven; K. A. A. Makinwa;
IEEE Journal of Solid-State Circuits,
Volume 56, Issue 4, pp. 1207-1215, January 2021. DOI: 10.1109/JSSC.2020.3044896
Abstract: ...
This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta–sigma modulator ( ΔΣM ) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC’s quantization noise into the audio band. The prototype ADC occupies 0.27 mm 2 in a 0.16- μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW . It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB.
T. Rooijers; S. Karmakar; Y. Kusuda; J. H. Huijsing; K. A. A. Makinwa;
In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
February 2021. DOI: 10.1109/ISSCC42613.2021.9365790
T. Rooijers; S. Karmakar; Y. Kusuda; J. H. Huijsing; K. A. A. Makinwa;
In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
pp. 438-440, February 2021. DOI: 10.1109/ISSCC42613.2021.9365790
H. Zhang; S. Karmakar; L. J. Breems; Q. Sandifort; M. Berkhout; K. A. A. Makinwa; Qinwen Fan;
IEEE Journal of Solid-State Circuits,
Volume 56, pp. 1176-1185, December 2020. DOI: 10.1109/JSSC.2020.3043815
Abstract: ...
This article presents a Class-D audio amplifier for automotive applications. Low electromagnetic interference (EMI) and, hence, smaller LC filter size are obtained by employing a fully differential multilevel output stage switching at 4.2 MHz. A modulation scheme with minimal switching activity at zero input reduces idle power, which is further assisted by a gate-charge reuse scheme. It also achieves high linearity due to the high loop gain realized by a third-order feedback loop with a bandwidth of 800 kHz. The prototype, fabricated in a 180-nm high-voltage BCD process, achieves a minimum THD+N of −107.8 dB/−102 dB and a peak efficiency of 91%/87% with 8- and 4- Ω loads, respectively, while drawing 7-mA quiescent current from a 14.4-V supply. The prototype meets the CISPR 25 Class 5 EMI standard with a 5.7-dB margin using an LC filter with a cutoff frequency of 580 kHz.
S. Karmakar; H. Zhang; R. van Veldhoven; L. J. Breems; M. Berkhout; Qinwen Fan; K. A. A. Makinwa;
IEEE Journal of Solid-State Circuits,
September 2020. DOI: 10.1109/JSSC.2020.3023874
Abstract: ...
This article presents a 28-W class-D amplifier for automotive applications. The combination of a high switching frequency and a hybrid multibit Δ ΣM-PWM scheme results in high linearity over a wide range of output power, as well as low AM-band EMI. As a result, only a small (150-kHz cutoff frequency), and thus low-cost, LC filter is needed to meet the CISPR-25 EMI average limit (150 kHz-30 MHz) with 10-dB margin. At 28-W output power, the proposed amplifier achieves 91% efficiency while driving a 4-Ω load from a 14.4-V supply. It attains a peak THD+N of 0.00077% (-102.2 dB) for a 1-kHz input signal.
Shoubhik Karmakar; Huajun Zhang; Robert van Veldhoven; Lucien J. Breems; Marco Berkhout; Qinwen Fan; Kofi A. A. Makinwa;
{IEEE} Journal of Solid-State Circuits,
Volume 55, Issue 12, pp. 3146--3156, December 2020. DOI: 10.1109/jssc.2020.3023874
document
Karmakar, Shoubhik; Zhang, Huajun; van Veldhoven, Robert; Breems, Lucien J.; Berkhout, Marco; Fan, Qinwen; Makinwa, Kofi A. A.;
IEEE Journal of Solid-State Circuits,
Volume 55, Issue 12, pp. 3146-3156, 2020. DOI: 10.1109/JSSC.2020.3023874
E. Eland; S. Karmakar; B. Gönen; R. van Veldhoven; K. Makinwa;
In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
June 2020. DOI: 10.1109/VLSICircuits18222.2020.9162856.
S. Karmakar; H. Zhang; R.Van Veldhoven; L. Breems; M. Berkhout; Qinwen Fan; K.A.A Makinwa;
In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
pp. 350-352, 2 2020. DOI: 10.1109/ISSCC19947.2020.9063001
H. Zhang; S. Karmakar; L. Breems; Q. Sandifort; M. Berkhout; K. Makinwa; Qinwen Fan;
In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
June 2020. DOI: 10.1109/VLSICircuits18222.2020.9162793
Huajun Zhang; Shoubhik Karmakar; Lucien Breems; Quino Sandifort; Marco Berkhout; Kofi Makinwa; Qinwen Fan;
In 2020 IEEE Symposium on VLSI Circuits,
United States, IEEE, pp. 1--2, 2020. Green Open Access added to TU Delft Institutional Repository {\textquoteleft}You share, we take care!{\textquoteright} – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher i. DOI: 10.1109/VLSICircuits18222.2020.9162793
Abstract: ...
This paper describes a class-D audio amplifier with a multilevel output stage that reduces both EMI and idle power. High loop gain, and thus high linearity, are enabled by a relatively high (4.2 MHz) switching frequency, which relaxes the requirements on its output LC filter. Fabricated in a 180nm BCD technology, it can drive 14 W into an 8-Ω load with state-of-the-art performance: -107.8 dB THD+N, 91% peak efficiency, and 7 mA quiescent current. It meets the CISPR 25 Class 5 radiated emission standard with a low-cost 580 kHz LC filter, improving the state-of-the-art by 5.8x.
Shoubhik Karmakar; Huajun Zhang; {Van Veldhoven}, Robert; Lucien Breems; Marco Berkhout; Qinwen Fan; Kofi A. A. Makinwa;
In 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020,
United States, IEEE, pp. 350--352, 2020. Green Open Access added to TU Delft Institutional Repository {\textquoteleft}You share, we take care!{\textquoteright} – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher i. DOI: 10.1109/ISSCC19947.2020.9063001
Abstract: ...
Class-D amplifiers are often used in high-power audio applications due to their high power efficiency. They typically employ pulse-width modulation (PWM) at a fixed carrier frequency, which may cause electromagnetic interference (EMI). Setting this frequency fPWM) below the AM band (535 to 1605kHz) helps mitigate this, but its harmonics still contain substantial energy and must be filtered out by bulky LC filters with low cut-off frequencies (fc = 20 to 40 kHz), significantly increasing system cost and size. Stability considerations also constrain the amplifier's unity-gain frequency to be < mathrm{f} {mathrm{PWM}}/pi [1], compromising the audio-band loop gain required to suppress output-stage nonlinearity. Setting fPWM above the AM band helps increase fc and allows a higher loop gain [2]. However, this results in narrower pulses at higher power levels (higher modulation index), which cannot be faithfully produced by the output stage, thus exacerbating its non-linearity. Delta-sigma modulation (DeltaSigma M) has fixed pulse widths and does not suffer from these narrow-pulse artefacts. However, the out-of-band noise of 1bit modulators then requires larger LC filters. Moreover, high-order loop filters must be used to achieve sufficient SQNR, which then require additional techniques to maintain stability as the modulation range approaches 100% [3].
Eland, Efraïm; Karmakar, Shoubhik; Gönen, Burak; van Veldhoven, Robert; Makinwa, Kofi;
In 2020 IEEE Symposium on VLSI Circuits,
pp. 1-2, 2020. DOI: 10.1109/VLSICircuits18222.2020.9162856
Zhang, Huajun; Karmakar, Shoubhik; Breems, Lucien; Sandifort, Quino; Berkhout, Marco; Makinwa, Kofi; Fan, Qinwen;
In 2020 IEEE Symposium on VLSI Circuits,
pp. 1-2, 2020. DOI: 10.1109/VLSICircuits18222.2020.9162793
Karmakar, Shoubhik; Zhang, Huajun; Van Veldhoven, Robert; Breems, Lucien; Berkhout, Marco; Fan, Qinwen; Makinwa, Kofi A.A.;
In 2020 IEEE International Solid-State Circuits Conference - (ISSCC),
pp. 350-352, 2020. DOI: 10.1109/ISSCC19947.2020.9063001
B. Gönen; S. Karmakar; R. van Veldhoven; K. A. A. Makinwa;
IEEE Journal of Solid-State Circuits,
Volume 55, pp. 1023-1031, 12 2019. DOI: 10.1109/JSSC.2019.2959480
Abstract: ...
This article presents a continuous-time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm 2 and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 μW. This results in a Schreier figure of merit (FoM) of 183.6 dB.
B. Gönen; S. Karmakar; R. van Veldhoven; K. A. A. Makinwa;
IEEE Journal of Solid-State Circuits,
Volume 55, Issue 4, pp. 1023-1031, 12 2019. DOI: 10.1109/JSSC.2019.2959480
Abstract: ...
This article presents a continuous-time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm 2 and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 μW. This results in a Schreier figure of merit (FoM) of 183.6 dB.
B. Gönen; S. Karmakar; R. van Veldhoven; K. A. A. Makinwa;
In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
6 2019. DOI: 10.23919/VLSIC.2019.8778021
B. Gönen; S. Karmakar; R. van Veldhoven; K. A. A. Makinwa;
In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
pp. C224-C225, 6 2019. DOI: 10.23919/VLSIC.2019.8778021
S. Karmakar; B. Gonen; F. Sebstiano; R. van Veldhoven; K. A. A. Makinwa;
IEEE Journal of Solid-State Circuits,
Volume 53, Issue 12, pp. 3497-3507, 12 2018. DOI: 10.1109/JSSC.2018.2865466
Abstract: ...
This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (<1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential ΔΣ ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16- μm CMOS process, the prototype occupies 0.26 mm 2 and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 μW . This results in a Schreier figure of merit (FoM) of 185.8 dB.
S. Karmakar; B. Gonen; F. Sebstiano; R. van Veldhoven; K. A. A. Makinwa;
IEEE Journal of Solid-State Circuits,
Volume 53, Issue 12, pp. 3497-3507, 12 2018. DOI: 10.1109/JSSC.2018.2865466
Abstract: ...
This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (<1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential ΔΣ ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16- μm CMOS process, the prototype occupies 0.26 mm 2 and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 μW . This results in a Schreier figure of merit (FoM) of 185.8 dB.
S. Karmakar; B. Gònen; F. Sebastiano; R. van Veldhoven; K.A.A. Makinwa;
In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
pp. 238-240, 2 2018. DOI: 10.1109/ISSCC.2018.8310272
S. Karmakar; B. Gònen; F. Sebastiano; R. van Veldhoven; K.A.A. Makinwa;
In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
pp. 238-240, 2 2018. DOI: 10.1109/ISSCC.2018.8310272
BibTeX support
Last updated: 20 Dec 2024
Shoubhik Karmakar
Alumnus- Left in 2022
MSc students
Alumni
- Efraïm Eland (EI) (2019)