MSc Karmakar

1. A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW
   E. Eland; S. Karmakar; B. Gönen; R. van Veldhoven; K. A. A. Makinwa;
   IEEE Journal of Solid-State Circuits,
   Volume 56, pp. 1207-1215, January 2021. DOI: 10.1109/JSSC.2020.3044896
   
   Abstract: ...

   This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta–sigma modulator ( ΔΣM ) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC’s quantization noise into the audio band. The prototype ADC occupies 0.27 mm 2 in a 0.16- μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW . It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB.

2. A Chopper-Stabilized Amplifier with -107dB IMD and 28dB Suppression of Chopper-Induced IMD
   T. Rooijers; S. Karmakar; Y. Kusuda; J. H. Huijsing; K. A. A. Makinwa;
   In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
   February 2021. DOI: 10.1109/ISSCC42613.2021.9365790

3. A 28-W, -102.2-dB THD+N Class-D Amplifier Using a Hybrid Δ Σ M-PWM Scheme
   S. Karmakar; H. Zhang; R. van Veldhoven; L. J. Breems; M. Berkhout; Q. Fan; K. A. A. Makinwa;
   IEEE Journal of Solid-State Circuits,
   September 2020. DOI: 10.1109/JSSC.2020.3023874
   
   Abstract: ...

   This article presents a 28-W class-D amplifier for automotive applications. The combination of a high switching frequency and a hybrid multibit Δ ΣM-PWM scheme results in high linearity over a wide range of output power, as well as low AM-band EMI. As a result, only a small (150-kHz cutoff frequency), and thus low-cost, LC filter is needed to meet the CISPR-25 EMI average limit (150 kHz-30 MHz) with 10-dB margin. At 28-W output power, the proposed amplifier achieves 91% efficiency while driving a 4-Ω load from a 14.4-V supply. It attains a peak THD+N of 0.00077% (-102.2 dB) for a 1-kHz input signal.

4. A High-Linearity and Low-EMI Multilevel Class-D Amplifier
   H. Zhang; S. Karmakar; L. J. Breems; Q. Sandifort; M. Berkhout; K. A. A. Makinwa; Q. Fan;
   IEEE Journal of Solid-State Circuits,
   Volume 56, pp. 1176-1185, December 2020. DOI: 10.1109/JSSC.2020.3043815
   
   Abstract: ...

   This article presents a Class-D audio amplifier for automotive applications. Low electromagnetic interference (EMI) and, hence, smaller LC filter size are obtained by employing a fully differential multilevel output stage switching at 4.2 MHz. A modulation scheme with minimal switching activity at zero input reduces idle power, which is further assisted by a gate-charge reuse scheme. It also achieves high linearity due to the high loop gain realized by a third-order feedback loop with a bandwidth of 800 kHz. The prototype, fabricated in a 180-nm high-voltage BCD process, achieves a minimum THD+N of −107.8 dB/−102 dB and a peak efficiency of 91%/87% with 8- and 4- Ω loads, respectively, while drawing 7-mA quiescent current from a 14.4-V supply. The prototype meets the CISPR 25 Class 5 EMI standard with a 5.7-dB margin using an LC filter with a cutoff frequency of 580 kHz.

5. A 28W -108.9dB/-102.2dB THD/THD+N Hybrid ΔΣ−PWM Class-D Audio Amplifier with 91% Peak Efficiency and Reduced EMI Emission
   S. Karmakar; H. Zhang; R.Van Veldhoven; L. Breems; M. Berkhout; Q. Fan; K.A.A Makinwa;
   In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
   pp. 350-352, 2 2020. DOI: 10.1109/ISSCC19947.2020.9063001

6. A −107.8 dB THD+N Low-EMI Multi-Level Class-D Audio Amplifier
   H. Zhang; S. Karmakar; L. Breems; Q. Sandifort; M. Berkhout; K. Makinwa; Q. Fan;
   In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
   June 2020. DOI: 10.1109/VLSICircuits18222.2020.9162793

7. A 440μW, 109.8dB DR, 106.5dB SNDR Discrete-Time Zoom ADC with a 20kHz BW
   E. Eland; S. Karmakar; B. Gönen; R. van Veldhoven; K. Makinwa;
   In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
   June 2020. DOI: 10.1109/VLSICircuits18222.2020.9162856.

8. A Low Power Continuous-Time Zoom ADC for Audio Applications
   B. Gönen; S. Karmakar; R. van Veldhoven; K. A. A. Makinwa;
   IEEE Journal of Solid-State Circuits,
   Volume 55, pp. 1023-1031, 12 2019. DOI: 10.1109/JSSC.2019.2959480
   
   Abstract: ...

   This article presents a continuous-time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm 2 and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 μW. This results in a Schreier figure of merit (FoM) of 183.6 dB.

9. A Low Power Continuous-Time Zoom ADC for Audio Applications
   B. Gönen; S. Karmakar; R. van Veldhoven; K. A. A. Makinwa;
   In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
   6 2019. DOI: 10.23919/VLSIC.2019.8778021

10. A 280μW Dynamic Zoom ADC With 120 dB DR and 118 dB SNDR in 1 kHz BW
    S. Karmakar; B. Gonen; F. Sebstiano; R. van Veldhoven; K. A. A. Makinwa;
    IEEE Journal of Solid-State Circuits,
    Volume 53, Issue 12, pp. 3497-3507, 12 2018. DOI: 10.1109/JSSC.2018.2865466
    
    Abstract: ...

    This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (<1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential ΔΣ ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16- μm CMOS process, the prototype occupies 0.26 mm 2 and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 μW . This results in a Schreier figure of merit (FoM) of 185.8 dB.

11. A 280μW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BWA 280μW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW
    S. Karmakar; B. Gònen; F. Sebastiano; R. van Veldhoven; K.A.A. Makinwa;
    In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
    pp. 238-240, 2 2018. DOI: 10.1109/ISSCC.2018.8310272

BibTeX support