MSc Karmakar

PhD student
Electronic Instrumentation (EI), Department of Microelectronics

Expertise: ADCs, High-Power Audio Amplifiers

Publications

  1. A 28W -108.9dB/-102.2dB THD/THD+N Hybrid ΔΣ−PWM Class-D Audio Amplifier with 91% Peak Efficiency and Reduced EMI Emission
    S. Karmakar; H. Zhang; R.Van Veldhoven; L. Breems; M. Berkhout; Q. Fan; K.A.A Makinwa;
    In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
    pp. 350-352, 2 2020. DOI: 10.1109/ISSCC19947.2020.9063001

  2. A Low Power Continuous-Time Zoom ADC for Audio Applications
    B. Gönen; S. Karmakar; R. van Veldhoven; K. A. A. Makinwa;
    IEEE Journal of Solid-State Circuits,
    Volume 55, pp. 1023-1031, 12 2019. DOI: 10.1109/JSSC.2019.2959480
    Abstract: ... This article presents a continuous-time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm 2 and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 μW. This results in a Schreier figure of merit (FoM) of 183.6 dB.

  3. A Low Power Continuous-Time Zoom ADC for Audio Applications
    B. Gönen; S. Karmakar; R. van Veldhoven; K. A. A. Makinwa;
    In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
    6 2019. DOI: 10.23919/VLSIC.2019.8778021

  4. A 280μW Dynamic Zoom ADC With 120 dB DR and 118 dB SNDR in 1 kHz BW
    S. Karmakar; B. Gonen; F. Sebstiano; R. van Veldhoven; K. A. A. Makinwa;
    IEEE Journal of Solid-State Circuits,
    Volume 53, Issue 12, pp. 3497-3507, 12 2018. DOI: 10.1109/JSSC.2018.2865466
    Abstract: ... This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (<1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential ΔΣ ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16- μm CMOS process, the prototype occupies 0.26 mm 2 and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 μW . This results in a Schreier figure of merit (FoM) of 185.8 dB.

  5. A 280μW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BWA 280μW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW
    S. Karmakar; B. Gònen; F. Sebastiano; R. van Veldhoven; K.A.A. Makinwa;
    In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
    pp. 238-240, 2 2018. DOI: 10.1109/ISSCC.2018.8310272

BibTeX support

Last updated: 2 Oct 2019

Shoubhik Karmakar

MSc students

  • Alumni

  • Efraïm Eland (2019)