MSc Patra

PhD student
Electronic Circuits and Architectures (ELCA), Department of Microelectronics

Themes: XG - Next Generation Sensing and Communication

Biography

Bishnu Patra (S’11) received the B.Tech. degree in electrical and electronics engineering from the International Institute of Information Technology Bhubaneswar, Bhubaneswar, India, in 2013, and the M.Sc. degree in electrical engineering (microelectronics) from the Delft University of Technology, Delft, The Netherlands, in 2016, where he is currently pursuing the Ph.D. degree in cryogenic RF circuits for quantum computing applications with the Quantum Engineering Department.

From 2013 to 2014, he was a B.Sc. Researcher with the ELCA Department. His current research interests include cryogenic RF transmitters for qubit control, cryogenic CMOS frequency synthesizers, such as phase-locked loop, oscillators, frequency dividers, and design and modeling of cryogenic microwave passive components.

Publications

  1. Benefits and challenges of designing cryogenic CMOS RF circuits for quantum computers
    Mehrpoo, M; Patra, B; Gong, J; van Dijk, JPG; Homulle, H; Kiene, G; Vladimirescu, A; Sebastiano, F; Charbon, E; Babaie, M; others;
    In 2019 IEEE International Symposium on Circuits and Systems (ISCAS),
    IEEE, pp. 1--5, 2019.

  2. Cryo-CMOS Circuits and Systems for Quantum Computing Applications
    Bishnu Patra; Rosario M. Incandela; Jeroen P. G. van Dijk; Harald A. R. Homulle; Lin Song; Mina Shahmohammadi; Robert B. Staszewski; Andrei Vladimirescu; Masoud Babaie; Fabio Sebastiano; Edoardo Charbon;
    IEEE Journal of Solid-State Circuits,
    Volume 53, Issue 1, pp. 1-13, Jan 2018. DOI: 10.1109/JSSC.2017.2737549
    Keywords: ... CMOS technology;Cryogenics;Oscillators;Process control;Quantum computing;Temperature;CMOS characterization;Class-F oscillator;cryo-CMOS;low-noise amplifier (LNA);noise canceling;phase noise (PN);quantum bit (qubit);quantum computing;qubit control;single-photon avalanche diode (SPAD)..

    Abstract: ... A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3 digitally controlled oscillator required to manipulate the state of qubits.

  3. Cryo-CMOS Circuits and Systems for Quantum Computing Applications
    B. Patra; R. M. Incandela; J. P. G. van Dijk; H. A. R. Homulle; L. Song; M. Shahmohammadi; R. B. Staszewski; A. Vladimirescu; M. Babaie; F. Sebastiano; E. Charbon;
    IEEE Journal of Solid-State Circuits,
    Volume 53, Issue 1, pp. 309-321, Jan 2018. DOI: 10.1109/JSSC.2017.2737549
    Keywords: ... CMOS technology;Cryogenics;Oscillators;Process control;Quantum computing;Temperature;CMOS characterization;Class-F oscillator;cryo-CMOS;low-noise amplifier (LNA);noise canceling;phase noise (PN);quantum bit (qubit);quantum computing;qubit control;single-photon avalanche diode (SPAD).

  4. A reconfigurable cryogenic platform for the classical control of quantum processors
    Harald Homulle; Stefan Visser; Bishnu Patra; Giorgio Ferrari; Enrico Prati; Fabio Sebastiano; Edoardo Charbon; Enrico Prati;
    Review of Scientific Instruments,
    Volume 88, Issue 4, pp. 045103, 2017. DOI: 10.1063/1.4979611
    Abstract: ... The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.} url={https://doi.org/10.1063/1.4979611

  5. Cryogenic CMOS interfaces for quantum devices
    Fabio Sebastiano; Harald A. R. Homulle; Jeroen P. G. van Dijk; Rosario M. Incandela; Bishnu Patra; M. Mehrpoo; Masoud Babaie; Andrei Vladimirescu; Edoardo Charbon;
    In 2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI),
    Vieste, Italy, pp. 59-62, June 2017. DOI: 10.1109/IWASI.2017.7974215
    Keywords: ... CMOS technology;Computers;Cryogenics;Process control;Quantum computing;Semiconductor device modeling;Standards;CMOS;cryo-CMOS;cryogenics;quantum computing;qubits.

    Abstract: ... Quantum computers could efficiently solve problems that are intractable by today's computers, thus offering the possibility to radically change entire industries and revolutionize our lives. A quantum computer comprises a quantum processor operating at cryogenic temperature and an electronic interface for its control, which is currently implemented at room temperature for the few qubits available today. However, this approach becomes impractical as the number of qubits grows towards the tens of thousands required for complex quantum algorithms with practical applications. We propose an electronic interface for sensing and controlling qubits operating at cryogenic temperature implemented in standard CMOS.

  6. Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited
    Fabio Sebastiano; Harald Homulle; Bishnu Patra; Rosario Incandela; Jeroen van Dijk; Lin Song; Masoud Babaie; Andrei Vladimirescu; Edoardo Charbon;
    In Proceedings of the 54th Annual Design Automation Conference 2017,
    New York, NY, USA, ACM, pp. 13:1--13:6, 2017. DOI: 10.1145/3061639.3072948
    Keywords: ... Cryo-CMOS, cryogenics, device models, error-correcting loop, quantum computation, qubit.

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  7. Cryo-CMOS circuits and systems for scalable quantum computing
    Edoardo Charbon; Fabio Sebastiano; Masoud Babaie; Andrei Vladimirescu; Mina Shahmohammadi; R. B. Staszewski; Harald A. R. Homulle; Bishnu Patra; Jeroen P. G. van Dijk; Rosario M. Incandela; Lin Song; Bahador Valizadehpasha;
    In 2017 IEEE International Solid-State Circuits Conference (ISSCC),
    pp. 264-265, Feb 2017. DOI: 10.1109/ISSCC.2017.7870362
    Keywords: ... CMOS integrated circuits;logic circuits;quantum computing;cryo-CMOS circuits;error-correcting loop;quantum algorithm;quantum bits arrays;quantum coherence loss;qubit states;room-temperature controller;scalable quantum computing;state-of-the-art quantum processors;unprecedented computation power;Cryogenics;Oscillators;Program processors;Quantum computing;Semiconductor device modeling;Substrates;Temperature sensors.

    Abstract: ... In Paper 15.5, Delft University of Technology, EPFL, and Intel present building blocks for a scalable CMOS interface to solid-state quantum processors with a projected efficiency of 200�W/qubit. The circuits include an analog noise-canceled 1.2GHz LNA with 28dB gain, a 6.2GHz class-F local oscillator with better than �145dBc/Hz phase noise at 10MHz offset, a 12µm SPAD with 0.1Hz dark count rate at 2V excess bias, and digital logic, all designed using ad hoc deep-cryogenic models.

  8. 15.5 Cryo-CMOS circuits and systems for scalable quantum computing
    E. Charbon; F. Sebastiano; M. Babaie; A. Vladimirescu; M. Shahmohammadi; R. B. Staszewski; H. A. R. Homulle; B. Patra; J. P. G. van Dijk; R. M. Incandela; L. Song; B. Valizadehpasha;
    In 2017 IEEE International Solid-State Circuits Conference (ISSCC),
    pp. 264-265, Feb 2017. DOI: 10.1109/ISSCC.2017.7870362
    Keywords: ... Cryogenics;Oscillators;Program processors;Quantum computing;Semiconductor device modeling;Substrates;Temperature sensors.

  9. Cryo-CMOS electronic control for scalable quantum computing
    Sebastiano, Fabio; Homulle, Harald; Patra, Bishnu; Incandela, Rosario; van Dijk, Jeroen; Song, Lin; Babaie, Masoud; Vladimirescu, Andrei; Charbon, Edoardo;
    In Proceedings of the 54th Annual Design Automation Conference 2017,
    pp. 1--6, 2017.

  10. Cryogenic CMOS interfaces for quantum devices
    Sebastiano, Fabio; Homulle, Harald AR; van Dijk, Jeroen PG; Incandela, Rosario M; Patra, Bishnu; Mehrpoo, Mohammadreza; Babaie, Masoud; Vladimirescu, Andrei; Charbon, Edoardo;
    In 2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI),
    IEEE, pp. 59--62, 2017.

  11. CryoCMOS Hardware Technology a Classical Infrastructure for a Scalable Quantum Computer
    Harald Homulle; Stefan Visser; Bishnu Patra; Giorgio Ferrari; Enrico Prati; Carmen G. Almud{\'e}ver; Koen Bertels; Fabio Sebastiano; Edoardo Charbon;
    In Proceedings of the ACM International Conference on Computing Frontiers,
    New York, NY, USA, ACM, pp. 282--287, 2016. DOI: 10.1145/2903150.2906828
    Keywords: ... (de)coherence, CryoCMOS, cryogenics, error-correcting loop, fault-tolerant computing, quantum computation, quantum micro-architecture, qubit.

    Abstract: ... We propose a classical infrastructure for a quantum computer implemented in CMOS. The peculiarity of the approach is to operate the classical CMOS circuits and systems at deep cryogenic temperatures (cryoCMOS), so as to ensure physical proximity to the quantum bits, thus reducing thermal gradients and increasing compactness. CryoCMOS technology leverages the CMOS fabrication infrastructure and exploits the continuous effort of miniaturization that has sustained Moores Law for over 50 years. Such approach is believed to enable the growth of the number of qubits operating in a fault-tolerant fashion, paving the way to scalable quantum computing machines.

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Last updated: 26 Dec 2018

Bishnu Patra