ir. H.A.R. Homulle

1. Benefits and challenges of designing cryogenic CMOS RF circuits for quantum computers
   Mehrpoo, M; Patra, B; Gong, J; van Dijk, JPG; Homulle, H; Kiene, G; Vladimirescu, A; Sebastiano, F; Charbon, E; Babaie, M; others;
   In 2019 IEEE International Symposium on Circuits and Systems (ISCAS),
   IEEE, pp. 1--5, 2019.

2. Cryo-CMOS Circuits and Systems for Quantum Computing Applications
   Bishnu Patra; Rosario M. Incandela; Jeroen P. G. van Dijk; Harald A. R. Homulle; Lin Song; Mina Shahmohammadi; Robert B. Staszewski; Andrei Vladimirescu; Masoud Babaie; Fabio Sebastiano; Edoardo Charbon;
   IEEE Journal of Solid-State Circuits,
   Volume 53, Issue 1, pp. 1-13, Jan 2018. DOI: 10.1109/JSSC.2017.2737549
   
   Keywords: ...

   CMOS technology;Cryogenics;Oscillators;Process control;Quantum computing;Temperature;CMOS characterization;Class-F oscillator;cryo-CMOS;low-noise amplifier (LNA);noise canceling;phase noise (PN);quantum bit (qubit);quantum computing;qubit control;single-photon avalanche diode (SPAD)..
   
   
   Abstract: ...

   A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3 digitally controlled oscillator required to manipulate the state of qubits.

3. Cryo-CMOS Circuits and Systems for Quantum Computing Applications
   B. Patra; R. M. Incandela; J. P. G. van Dijk; H. A. R. Homulle; L. Song; M. Shahmohammadi; R. B. Staszewski; A. Vladimirescu; M. Babaie; F. Sebastiano; E. Charbon;
   IEEE Journal of Solid-State Circuits,
   Volume 53, Issue 1, pp. 309-321, Jan 2018. DOI: 10.1109/JSSC.2017.2737549
   
   Keywords: ...

   CMOS technology;Cryogenics;Oscillators;Process control;Quantum computing;Temperature;CMOS characterization;Class-F oscillator;cryo-CMOS;low-noise amplifier (LNA);noise canceling;phase noise (PN);quantum bit (qubit);quantum computing;qubit control;single-photon avalanche diode (SPAD).

4. A reconfigurable cryogenic platform for the classical control of quantum processors
   Harald Homulle; Stefan Visser; Bishnu Patra; Giorgio Ferrari; Enrico Prati; Fabio Sebastiano; Edoardo Charbon; Enrico Prati;
   Review of Scientific Instruments,
   Volume 88, Issue 4, pp. 045103, 2017. DOI: 10.1063/1.4979611
   
   Abstract: ...

   The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.} url={https://doi.org/10.1063/1.4979611

5. Cryogenic CMOS interfaces for quantum devices
   Fabio Sebastiano; Harald A. R. Homulle; Jeroen P. G. van Dijk; Rosario M. Incandela; Bishnu Patra; M. Mehrpoo; Masoud Babaie; Andrei Vladimirescu; Edoardo Charbon;
   In 2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI),
   Vieste, Italy, pp. 59-62, June 2017. DOI: 10.1109/IWASI.2017.7974215
   
   Keywords: ...

   CMOS technology;Computers;Cryogenics;Process control;Quantum computing;Semiconductor device modeling;Standards;CMOS;cryo-CMOS;cryogenics;quantum computing;qubits.
   
   
   Abstract: ...

   Quantum computers could efficiently solve problems that are intractable by today's computers, thus offering the possibility to radically change entire industries and revolutionize our lives. A quantum computer comprises a quantum processor operating at cryogenic temperature and an electronic interface for its control, which is currently implemented at room temperature for the few qubits available today. However, this approach becomes impractical as the number of qubits grows towards the tens of thousands required for complex quantum algorithms with practical applications. We propose an electronic interface for sensing and controlling qubits operating at cryogenic temperature implemented in standard CMOS.

6. Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited
   Fabio Sebastiano; Harald Homulle; Bishnu Patra; Rosario Incandela; Jeroen van Dijk; Lin Song; Masoud Babaie; Andrei Vladimirescu; Edoardo Charbon;
   In Proceedings of the 54th Annual Design Automation Conference 2017,
   New York, NY, USA, ACM, pp. 13:1--13:6, 2017. DOI: 10.1145/3061639.3072948
   
   Keywords: ...

   Cryo-CMOS, cryogenics, device models, error-correcting loop, quantum computation, qubit.
   
   document

7. Cryo-CMOS circuits and systems for scalable quantum computing
   Edoardo Charbon; Fabio Sebastiano; Masoud Babaie; Andrei Vladimirescu; Mina Shahmohammadi; R. B. Staszewski; Harald A. R. Homulle; Bishnu Patra; Jeroen P. G. van Dijk; Rosario M. Incandela; Lin Song; Bahador Valizadehpasha;
   In 2017 IEEE International Solid-State Circuits Conference (ISSCC),
   pp. 264-265, Feb 2017. DOI: 10.1109/ISSCC.2017.7870362
   
   Keywords: ...

   CMOS integrated circuits;logic circuits;quantum computing;cryo-CMOS circuits;error-correcting loop;quantum algorithm;quantum bits arrays;quantum coherence loss;qubit states;room-temperature controller;scalable quantum computing;state-of-the-art quantum processors;unprecedented computation power;Cryogenics;Oscillators;Program processors;Quantum computing;Semiconductor device modeling;Substrates;Temperature sensors.
   
   
   Abstract: ...

   In Paper 15.5, Delft University of Technology, EPFL, and Intel present building blocks for a scalable CMOS interface to solid-state quantum processors with a projected efficiency of 200�W/qubit. The circuits include an analog noise-canceled 1.2GHz LNA with 28dB gain, a 6.2GHz class-F local oscillator with better than �145dBc/Hz phase noise at 10MHz offset, a 12µm SPAD with 0.1Hz dark count rate at 2V excess bias, and digital logic, all designed using ad hoc deep-cryogenic models.

8. Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures
   R. M. Incandela; L. Song; H. A. R. Homulle; F. Sebastiano; E. Charbon; A. Vladimirescu;
   In 2017 47th European Solid-State Device Research Conference (ESSDERC),
   pp. 58-61, Sept 2017. DOI: 10.1109/ESSDERC.2017.8066591
   
   Keywords: ...

   CMOS integrated circuits;cryogenic electronics;integrated circuit modelling;nanoelectronics;augmented MOS11/PSP model;deep-cryogenic temperatures;nanometer CMOS transistors;size 160.0 nm;standard CMOS technologies;temperature 100.0 mK;temperature 4.0 K;Cryogenics;Current measurement;MOS devices;Performance evaluation;Semiconductor device modeling;Transistors.

9. 15.5 Cryo-CMOS circuits and systems for scalable quantum computing
   E. Charbon; F. Sebastiano; M. Babaie; A. Vladimirescu; M. Shahmohammadi; R. B. Staszewski; H. A. R. Homulle; B. Patra; J. P. G. van Dijk; R. M. Incandela; L. Song; B. Valizadehpasha;
   In 2017 IEEE International Solid-State Circuits Conference (ISSCC),
   pp. 264-265, Feb 2017. DOI: 10.1109/ISSCC.2017.7870362
   
   Keywords: ...

   Cryogenics;Oscillators;Program processors;Quantum computing;Semiconductor device modeling;Substrates;Temperature sensors.

10. Cryo-CMOS electronic control for scalable quantum computing
    Sebastiano, Fabio; Homulle, Harald; Patra, Bishnu; Incandela, Rosario; van Dijk, Jeroen; Song, Lin; Babaie, Masoud; Vladimirescu, Andrei; Charbon, Edoardo;
    In Proceedings of the 54th Annual Design Automation Conference 2017,
    pp. 1--6, 2017.

11. Cryogenic CMOS interfaces for quantum devices
    Sebastiano, Fabio; Homulle, Harald AR; van Dijk, Jeroen PG; Incandela, Rosario M; Patra, Bishnu; Mehrpoo, Mohammadreza; Babaie, Masoud; Vladimirescu, Andrei; Charbon, Edoardo;
    In 2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI),
    IEEE, pp. 59--62, 2017.

12. Tunable single hole regime of a silicon field effect transistor in standard CMOS technolog
    Marco Turchetti; Harald Homulle; Fabio Sebastiano; Giorgio Ferrari; Edoardo Charbon; Enrico Prati;
    Applied Physics Express,
    Volume 9, Issue 1, pp. 014001, 2016. DOI: 10.7567/APEX.9.014001
    
    Abstract: ...

    The electrical properties of a Single Hole Field Effect Transistor (SH-FET) based on CMOS technology are analyzed in a cryogenic environment. Few electron?hole Coulomb diamonds are observed using quantum transport spectroscopy measurements, down to the limit of single hole transport. Controlling the hole filling of the SH-FET is made possible by biasing the top gate, while the bulk contact is employed as a back gate that tunes the hole state coupling with the contacts and their distance from the interface. We compare the cryogenic Coulomb blockade regime with the room temperature regime, where the device operation is similar to that of a standard p-MOSFET.
    
    document

13. Cryo-CMOS for Quantum Computing
    E. Charbon; F. Sebastiano; A. Vladimirescu; H. Homulle; S. Visser; L. Song; R. Incandela;
    In Internation Electon Devices Meeting (IEDM),
    December 2016.

14. Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS
    L. Song; H. Homulle; E. Charbon; F. Sebastiano;
    In IEEE Sensors 2016,
    October 2016.

15. CryoCMOS Hardware Technology a Classical Infrastructure for a Scalable Quantum Computer
    Harald Homulle; Stefan Visser; Bishnu Patra; Giorgio Ferrari; Enrico Prati; Carmen G. Almud{\'e}ver; Koen Bertels; Fabio Sebastiano; Edoardo Charbon;
    In Proceedings of the ACM International Conference on Computing Frontiers,
    New York, NY, USA, ACM, pp. 282--287, 2016. DOI: 10.1145/2903150.2906828
    
    Keywords: ...

    (de)coherence, CryoCMOS, cryogenics, error-correcting loop, fault-tolerant computing, quantum computation, quantum micro-architecture, qubit.
    
    
    Abstract: ...

    We propose a classical infrastructure for a quantum computer implemented in CMOS. The peculiarity of the approach is to operate the classical CMOS circuits and systems at deep cryogenic temperatures (cryoCMOS), so as to ensure physical proximity to the quantum bits, thus reducing thermal gradients and increasing compactness. CryoCMOS technology leverages the CMOS fabrication infrastructure and exploits the continuous effort of miniaturization that has sustained Moore?s Law for over 50 years. Such approach is believed to enable the growth of the number of qubits operating in a fault-tolerant fashion, paving the way to scalable quantum computing machines.
    
    document

16. Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS
    Lin Song; Harald Homulle; Edoardo Charbon; Fabio Sebastiano;
    In IEEE Sensors 2016,
    pp. 1-3, October 2016. DOI: 10.1109/ICSENS.2016.7808759
    
    Keywords: ...

    CMOS integrated circuits;bipolar transistors;cryogenics;temperature sensors;CMOS integrated temperature sensors;bipolar substrate PNP;bipolar transistors;carrier freeze-out;cryogenic temperature sensors;finite current gain;parasitic base resistance;size 160 nm;standard CMOS;temperature 7 K to 298 K;CMOS technology;Cryogenics;Standards;Substrates;Temperature distribution;Temperature sensors;CMOS;cryogenics;substrate bipolar transistors;temperature sensors.
    
    
    Abstract: ...

    This paper presents the cryogenic characterization of the bipolar substrate PNPs that are typically employed as sensing elements in CMOS integrated temperature sensors. PNPs realized in a standard 160-nm CMOS technology were characterized over the temperature range from 7 K to 294 K. Although PNP non-idealities, such as finite current gain and parasitic base resistance, deteriorate at lower temperature, device operation similar to room temperature is observed down to 70 K, while operation at lower temperatures is limited by carrier freeze-out in the base region and limited current gain. These results demonstrate the feasibility of temperature sensors in standard CMOS at cryogenic temperature.

17. Cryo-CMOS for quantum computing
    Edoardo Charbon; Fabio Sebastiano; Andrei Vladimirescu; Harald Homulle; Stefan Visser; Lin Song; Rosario M. Incandela;
    In Proc. 2016 IEEE International Electron Devices Meeting (IEDM),
    pp. 13.5.1-13.5.4, Dec 2016. DOI: 10.1109/IEDM.2016.7838410
    
    Keywords: ...

    CMOS integrated circuits;VLSI;cryogenic electronics;fault tolerance;integrated circuit design;integrated circuit reliability;quantum computing;VLSI design;cryoCMOS;cryogenic CMOS circuits;cryogenic CMOS systems;deep-cryogenic temperatures;fault-tolerant quantum bits;fault-tolerant qubit system;quantum computing;Computers;Fault tolerance;Fault tolerant systems;Field programmable gate arrays;Multiplexing;Quantum computing;Quantum dots.
    
    
    Abstract: ...

    Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.

18. 200 MS/s ADC implemented in a FPGA employing TDCs
    H. Homulle; F. Regazzoni; E. Charbon;
    In International Symposium on Field-Programmable Gate Arrays,
    Feb. 2015.
    document

19. Fluorescence lifetime imaging to differentiate bound from unbound ICG-cRGD both in vitro and in vivo
    P.L. Stegehuis; M.C. Boonstra; F.E. Powolny; R. Sinisi; H. Homulle; C. Bruschini; E. Charbon; C.J.H. van de Velde; B.P.F. Lelieveldt; A.L. Vahrmeijer; J. Dijkstra; M. van de Giessen;
    In SPIE,
    Feb. 2015.
    document

20. Time-resolved imaging system for fluorescence-guided surgery with lifetime imaging capability
    F. Powolny; K. Homicsko; R. Sinisi; Claudio E. Bruschini; E. Grigoriev; H. Homulle; John O. Prior; D. Hanahan; E. Dubikovskaya; E. Charbon;
    In Proc. SPIE,
    pp. 912938, May 2014.

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