# Agenda

## PhD thesis defence Yao Liu

- Tuesday, 13 June 2017
- 14:30-16:00
- Aula, Senaatszaal

### Analysis and Design of Low-Power Receivers: Exploiting Non-50-Ohm Antenna Impedance and Phase-Only Quantization

**Yao Liu**

**Summary**

Reducing the power consumption of low-power short-range receivers is of critical importance for biomedical and Internet-of-Things applications. Two interesting degrees of freedom (or properties) that have not been fully exploited in the pursuit of low power consumption are the antenna impedance and the phase-only modulation property of FSK/PSK signals. This dissertation explores the possibility of reducing the power consumption of the receiver by utilizing these two degrees of freedom.

The feasibility of using a non-50-ohm antenna impedance in an active receiver front-end is first studied. A general antenna-electronics interface analysis is carried out, suggesting that power transfer is not the only design objective in the interface, but that the impedances of antenna and load need to be optimized for either voltage or current, depending on which is more favorable to measure with the electronics. This principle has been applied to a co-design example of an inductive antenna impedance and a low-noise amplifier (LNA). A passive RF gain can be achieved by using the proposed principle, and hence the noise figure (NF) can be reduced without sacrificing power consumption. The concept of a non-50-ohm antenna impedance is also exploited in the context of passive front-ends (PFEs). An inductive antenna impedance proves beneficial for increasing the passive voltage gain of an antenna-LNA interface. The study of the PFE aims for the same voltage-boosting effect by incorporating the inductive antenna impedance in the PFE. An analysis reveals that the inductive antenna impedance introduces two extra degrees of freedom to increase the downconverted voltage of the front-end for a given antenna available power. In order to well maintain the passive gain offered by the inductive antenna impedance together with its resonant load, the passive mixer should present a high-quality-factor capacitive input. This is achieved by incorporating an intermediate inductance in the passive network. The proposed front-end and a baseband LNA have been implemented to verify the voltage-boosting effect. The implementation has a passive gain of 11.6 dB, which is close to the state-of-the-art of 12 dB.

A promising concept which can fully utilize the phase-only modulation property of FSK/PSK signals is that of phase-domain analog-to-digital converters (PhADCs). This dissertation also deals with the analysis and design of PhADCs. First of all, analytical methods are proposed to comprehensively compare the PhADC and an (in-phase and quadrature) IQ ADC. Phase signal-to-noise ratio (SNR) expressions of the two ADC types are formulated analytically to facilitate a quantitative comparison of the ADCs. In comparison with the IQ ADC, the PhADC, due to its embedded demodulation attribute, is a more compact quantization and demodulation solution when interference accommodation is not required. Moreover, considering a flash ADC as an example of the low resolution (3-4 bit) IQ ADC, the PhADC has a lower theoretical energy limit than the flash IQ ADC for a given phase effective number of bits (ENOB) due to the immunity to magnitude variations and the phase-only quantization, thereby showing the great room for energy efficiency improvement that the PhADC has. Second, having discussed the interesting attributes of the PhADC, an IQ-assisted conversion algorithm and a corresponding circuit topology to improve the energy efficiency of the PhADC are proposed. Thanks to the successive approximation (SAR)-like algorithm and charge-domain operation, the prototype achieves a FoM of 1.2 pJ/step, which is better than the state-of-the-art of 8.3 pJ/step. Finally, the explicit relationship between the input amplitude SNR and the output phase SNR of the PhADC has been formulated. This relationship facilitates the system analysis of a receiver using a PhADC.

Using the proposed PFE and charge-redistribution PhADC, a receiver system is constructed. Based on the measured specifications of the PFE and the PhADC, the simulated performance of a PGA and a 2nd-order filter and the analysis outcomes of the PhADC presented in Chapter 4, the benefit of using the PhADC for a receiver system is quantified. For the proposed PFE and the IEEE 802.15.6 application, two ADCs (for I and Q paths) with a SNR of 30.4 dB are needed if an amplitude ADC is used, while a PhADC with a phase SNR of 24.5 dB (when the input amplitude is -11.9 dBm) is sufficient if a PhADC is used. For an antenna input level of -83.6 dBm (which corresponds to the minimum input level that has been specified for the PhADC), the presented receiver system demonstrates a sufficient overall SNR for the IEEE 802.15.6 standard, thereby paving the way to fully-integrated low-power receivers for the standard.

Additional information ...### Agenda

- Tue, 21 Nov 2017
- 12:00
- EKL colloquiumroom

### MSc ME Thesis Presentation

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- Tue, 28 Nov 2017
- 10:00
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### MSc ME Thesis Presentation

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#### FPGA based real time detection and signal, processing of electric nanosecond Partial Discharge (PD) pulses to extract parameters facilitating PD classication.

- 14 -- 16 May 2018
- Edinburgh

#### 27th Workshop on Advances in Analog Circuit Design

The AACD workshops are a high-quality series of events held all over the world.