prof.dr. K Bult

1. A Resistive Degeneration Technique for Linearizing Open-Loop Amplifiers
   M. S. Akter; R. Sehgal; K. Bult;
   IEEE Transactions on Circuits and Systems II: Express Briefs,
   Volume 67, Issue 11, pp. 2322-2326, 2020. DOI: 10.1109/TCSII.2020.2966276

2. Low-Power Analog Techniques, Sensors for Mobile Devices, and Energy Efficient Amplifiers
   K. Bult; M. S. Akter; R. Sehgal;
   Springer, Chapter High-efficiency, , pp. 253-296, 2019.

3. A Capacitively-Degenerated 100dB Linear 20-150MS/s Dynamic Amplifier
   M. S. Akter; K.A.A. Makinwa; K. Bult;
   IEEE Journal of Solid-State Circuits,
   Volume 53, pp. 1115 - 1126, 4 2018. DOI: 10.1109/JSSC.2017.2778277
   
   Abstract: ...

   This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mVpp,diff and 4x gain, it achieves -100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 μW at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26x compared with that of state-of-the-art high-linearity amplifiers.

4. A 66 dB SNDR Pipelined Split-ADC in 40 nm CMOS Using a Class-AB Residue Amplifier
   M. S. Akter; R. Sehgal; F. van der Goes; K. A. A. Makinwa; K. Bult;
   IEEE Journal of Solid-State Circuits,
   Volume 53, pp. 2939-2950, 10 2018. DOI: 10.1109/JSSC.2018.2859415
   
   Abstract: ...

   This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push–pull structure with a “split-capacitor” biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still maintaining sufficient linearity. This also allows the amplifier’s gain to be corrected by adjusting its bias current. When combined with digital gain-error detection, in this case the split-ADC technique, the result is a power-efficient gain calibration scheme. In a prototype pipelined ADC, this scheme converges in only 12 000 clock cycles. With a near-Nyquist input, the ADC achieves 66-dB SNDR and 77.3-dB SFDR at 53 MS/s. Implemented in 40-nm CMOS, it dissipates 9 mW, of which 0.83 mW is consumed in the residue amplifiers. This represents a 1.8 × improvement in power efficiency compared to state-of-the-art class-AB residue amplifiers.

5. A Capacitively-Degenerated 100dB Linear 20-150MS/s Dynamic Amplifier
   M. S. Akter; K.A.A. Makinwa; K. Bult;
   IEEE Journal of Solid-State Circuits,
   Volume 53, Issue 4, pp. 1115 - 1126, 4 2018. DOI: 10.1109/JSSC.2017.2778277
   
   Abstract: ...

   This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mVpp,diff and 4x gain, it achieves -100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 μW at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26x compared with that of state-of-the-art high-linearity amplifiers.

6. A 66 dB SNDR Pipelined Split-ADC in 40 nm CMOS Using a Class-AB Residue Amplifier
   M. S. Akter; R. Sehgal; F. van der Goes; K. A. A. Makinwa; K. Bult;
   IEEE Journal of Solid-State Circuits,
   Volume 53, Issue 10, pp. 2939-2950, 10 2018. DOI: 10.1109/JSSC.2018.2859415
   
   Abstract: ...

   This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push–pull structure with a “split-capacitor” biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still maintaining sufficient linearity. This also allows the amplifier’s gain to be corrected by adjusting its bias current. When combined with digital gain-error detection, in this case the split-ADC technique, the result is a power-efficient gain calibration scheme. In a prototype pipelined ADC, this scheme converges in only 12 000 clock cycles. With a near-Nyquist input, the ADC achieves 66-dB SNDR and 77.3-dB SFDR at 53 MS/s. Implemented in 40-nm CMOS, it dissipates 9 mW, of which 0.83 mW is consumed in the residue amplifiers. This represents a 1.8 × improvement in power efficiency compared to state-of-the-art class-AB residue amplifiers.

7. A Capacitively-Degenerated 100dB Linear 20-150MS/s Dynamic Amplifier
   M. S. Akter; K.A.A. Makinwa; K. Bult;
   In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
   6 2017. DOI: 10.23919/vlsic.2017.8008459

8. A Capacitively-Degenerated 100dB Linear 20-150MS/s Dynamic Amplifier
   M. S. Akter; K.A.A. Makinwa; K. Bult;
   In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
   pp. C136-C137, 6 2017. DOI: 10.23919/vlsic.2017.8008459

9. A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction
   M. S. Akter; R. Sehgal; F. van der Goes; K. Bult;
   In proc. ESSCIRC,
   pp. 315-318, 2015. DOI: 10.1109/ESSCIRC.2015.7313890

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