MSc A.R. Ximenes
Electronic Circuits and Architectures (ELCA), Department of Microelectronics
Promotor: Bogdan Staszewski, Edoardo Charbon
Expertise: RF IC design
Augusto Ronchini Ximenes is a Ph.D. candidate researcher at TU Delft since April 2012. He received his MSc degree in Electrical Engineering at State University of Campinas, Campinas in Brazil in July 2011.
His research interests are: RF integrated circuits design; Microelectronics; Advanced analog integrated circuit design; Different topologies for LNA, active and passive mixers and power amplifiers, both for low power applications.
- A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS
Chao-Chieh Li; T. H. Tsai; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo; K. Hsieh; M. Chen; A. Ximenes; R. B. Staszewski;
In 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits),
pp. 1-2, June 2016. DOI: 10.1109/VLSIC.2016.7573551
Keywords: ...CMOS integrated circuits;MOSFET circuits;digital phase locked loops;transformers;DCO;FinFET CMOS;LC-tank-based ADPLL;capacitor banks;fractional-N all-digital PLL;frequency 10.8 GHz to 19.3 GHz;frequency reference clock;inverter-based ring-oscillator PLL;magnetic coupling transformer;metastability-resolution scheme;size 10 nm;time 725 fs;Capacitors;Clocks;FinFETs;Jitter;Phase locked loops;Q-factor;Tuning.
Last updated: 19 Aug 2019