Amir Zjajo

1. A sub-nW neuromorphic receptors for wide-range temporal patterns of post-synaptic responses in 65 nm CMOS
   X. You; A. Zjajo; S. Kumar; R. van Leuken;
   Analog Integrated Circuits and Signal Processing,
   2018. DOI: 10.1007/s10470-018-1276-4
   document

2. A real-time reconfigurable architecture for large-scale biophysically-accurate neuron simulation
   A. Zjajo; J. Hofmann; G.J. Christiaanse; M. van Eijk; G. Smaragdos; C. Strydis; A. de Graaf; C. Galuzzi; R. van Leuken;
   IEEE Transactions on Biomedical Circuits and Systems,
   Volume 12, Issue 2, pp. 326-337, 2018. DOI: 10.1109/TBCAS.2017.2780287
   document

3. Real-Time Multi-Chip Neural Network for Cognitive Systems
   A. Zjajo; R. van Leuken (Ed.);
   Delft, The Netherlands: River Publishers, , 2018. ISBN 978-87-702-2034-7.
   document

4. Energy-Efficient Multipath Ring Network for Heterogeneous Clustered Neuronal Arrays
   A. Ardelean; A. Zjajo; S.S. Kumar; R. van Leuken;
   In IEEE Biomedical and Health Informatics (BHI),
   Las Vegas (USA), IEEE, pp. 190-193, March 2018. DOI: 10.1109/BHI.2018.8333401
   document

5. Multi-layer neuromorphic synapse for reconfigurable networks
   A. Zjajo; S. Kumar; R. van Leuken;
   In IEEE International Conference on Signal Processing,
   Beijing, China, pp. 997-1000, 2018.
   document

6. Uncertainty in noise-driven steady-state neuromorphic network for ECG data classificaiton
   A. Zjajo; J. Mes; E. Kolagasiogly; S. Kumar; R. van Leuken;
   In IEEE International Symposium on Computer Based Medical Systems,
   Karlstad, Sweden, pp. 434-435, 2018. ISSN 2372-9198. DOI: 10.1109/CBMS.2018.00082
   document

7. Fighting Dark Silicon: Toward Realizing Efficient Thermal-Aware 3-D Stacked Multiprocessors
   S.S. Kumar; A. Zjajo; T.G.R.M. van Leuken;
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
   Volume 25, Issue 4, pp. 1549-1562, 2017. ISSN 1063-8210. DOI: 10.1109/TVLSI.2016.2642587
   document

8. Immediate Neighborhood Temperature Adaptive Routing for Dynamically Throttled 3-D Networks-on-Chip
   S. S. Kumar; A. Zjajo; R. van Leuken;
   IEEE Transactions on Circuits and Systems II: Express Briefs,
   Volume 64, Issue 7, pp. 782-786, July 2017. ISSN 1549-7747. DOI: 10.1109/TCSII.2015.2503613
   document

9. Digital Spiking Neuron Cells for Real-Time Reconfigurable Learning Networks
   Haipeng Lin; A. Zjajo; R. van Leuken;
   In 30th IEEE International System-on-Chip Conference (SOCC),
   Arlington (VA), September 2017. DOI: 10.1109/SOCC.2017.8226029
   document

10. Neuromorphic spike data classifier for reconfigurable brain-machine interface
    A. Zjajo; S. Kumar; R. van Leuken;
    In 2017 8th International IEEE/EMBS Conference on Neural Engineering (NER),
    pp. 150-153, May 2017. DOI: 10.1109/NER.2017.8008314
    document

11. Neuromorphic Self-Organizing Map Design for Classification of Bioelectric-Timescale Signals
    J. Mes; E. Stienstra; Xuefei You; S. Kumar; A. Zjajo; C. Galuzzi; R. van Leuken;
    In Int. Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XVII),
    July 2017.

12. Energy-Efficient Neuromorphic Receptors for Wide-Range Temporal Patterns of Post-Synaptic Responses
    Xuefei You; A. Zjajo; S. S. Kumar; R. van Leuken;
    In IEEE Nordic Circuits and Systems Conference (2017 NorCAS),
    Linkoping (Sweden), October 2017. DOI: 10.1109/NORCHIP.2017.8124951
    document

13. Power-Efficiency of Signal Processing Circuits in Implantable Multichannel Brain-Machine Interface
    A. Zjajo;
    Journal of Low Power Electronics,
    Volume 12, Issue 4, pp. 342-351, 2016.
    document

14. Brain-Machine Interface: circuits and systems
    A. Zjajo;
    Switzerland: Springer, , 2016. DOI: 10.1007/978-3-319-31541-6
    document

15. Exploration of the thermal design space in 3D integrated circuits
    S.S. Kumar; A. Zjajo; R. van Leuken;
    In Physical Design for 3D Integrated Circuits,
    CRC Press, 2016. ISBN: 978-1-4987-1037-4.

16. Thermal expansion and aging effects in neuromorphic signal processor
    A. Zjajo; R. van Leuken;
    In Nanoelectronics Conference (INEC), 2016 IEEE International,
    Chengdu, China, IEEE, pp. 1--2, 2016. DOI: 10.1109/INEC.2016.7589259
    document

17. A 2.7 muW 10b 640kS/s time-based A/D converter for implantable neural recording interface
    A. Zjajo; S. Astigimath; R. van Leuken;
    In Circuits and Systems (ISCAS), 2016 IEEE International Symposium on,
    IEEE, pp. 1074--1077, 2016. DOI: 10.1109/ISCAS.2016.7527430
    document

18. A 2.1 muW/channel current-mode integrated neural recording interface
    A. Zjajo; R. van Leuken;
    In 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics (BHI),
    IEEE, pp. 505--508, 2016. DOI: 10.1109/BHI.2016.7455945
    document

19. A 41 muW real-time adaptive neural spike classifier
    A. Zjajo; R. van Leuken;
    In 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics (BHI),
    IEEE, pp. 489--492, 2016. DOI: 10.1109/BHI.2016.7455941
    document

20. A real-time hybrid neuron network for highly parallel cognitive systems
    G.J. Christiaanse; A. Zjajo; C. Galuzzi; R. van Leuken;
    In Engineering in Medicine and Biology Society (EMBC), 2016 IEEE 38th Annual International Conference of the,
    IEEE, pp. 792--795, 2016. DOI: 10.1109/EMBC.2016.7590820
    document

21. Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation
    J. Hofmann; A. Zjajo; C. Galuzzi; R. van Leuken;
    In IEEE International Conference of the IEEE Engineering in Medicine and Biology Society,
    Orlando, Florida, pp. 5829-5832, 2016.
    document

22. Immediate neighborhood temperature adaptive routing for 3D networks-on-chip
    S. Kumar; A. Zjajo; R. van Leuken;
    IEEE Transactions on Circuits and Systems-II: Express Briefs,
    2015. DOI: 10.1109/TCSII.2015.2503613
    document

23. Thermal Design of 3D Systems-on-Chip
    S. S. Kumar; A. Zjajo; R. van Leuken;
    In Physical Design for 3D Integrated Circuits,
    CRC Press, 2015. DOI: 978-87-929-8271-1
    document

24. Physical characterization of steady-state temperature profiles in three-dimensional integrated circuits
    S. Kumar; A. Zjajo; R. van Leuken;
    In IEEE International Symposium on Circuits and Systems,
    Lisbon, Portugal, pp. pp. 1969-1972, 2015.
    document

25. Ctherm: A integrated framework for thermal-functional co-simulation of systems-on-chip
    S. Kumar; A. Zjajo; R. van Leuken;
    In IEEE International Conference on Parallel, Distributed and Network-based Processing,
    Turku, Finland, pp. pp. 674-681, 2015.
    document

26. Multi-domain SystemC model of 128-channel time-multiplexed brain-machine interface
    K. Wirianto; A. Zjajo; C. Galuzzi; R. van Leuken;
    In IEEE International Conference on Embedded Computer Systems,
    Samos, Greece, pp. pp. 295-302, 2015.
    document

27. Noise analysis of programmable gain analog to digital converter for integrated neural implant front end
    A. Zjajo; C. Galuzzi; R. van Leuken;
    In IEEE International Conference on Biomedical Electronics and Devices,
    Lisbon, Portugal, pp. pp. 5-12, 2015.
    document

28. Stochastic noise analysis of neural interface front end
    A. Zjajo; C. Galuzzi; R. van Leuken;
    In IEEE International Symposium on Circuits and Systems,
    Lisbon, Portugal, pp. pp. 169-172, 2015.
    document

29. Sequential power per area optimization of multichannel neural recording interface based on dual quadratic programming
    A. Zjajo; C. Galuzzi; R. van Leuken;
    In IEEE International Conference on Neural Engineering,
    Montpellier, France, pp. pp. 9-12, 2015.
    document

30. A 31 pJ/spike hybrid stochastic neuromorphic signal processor
    A. Zjajo; C. Galuzzi; R. van Leuken;
    In IEEE Signal Processing in Medicine and Biology Symposium,
    Philadelphia, USA, pp. pp. 1-2, 2015.
    document

31. Frequency response mismatch correction in multichannel time interleaved analog bemformers for ultrasound medical imaging
    A. Zjajo; R. van Leuken;
    In IEEE International Conference on Bioinformatics and Biomedical Engineering,
    Shangai, China, pp. pp. 341-348, 2015.
    document

32. Iterative learning cascaded multiclass kernel based support vector machine for neural spike data classification
    A. Zjajo; and R. van Leuken;
    In IEEE International Conference on Computational Intelligence in Bioinformatics and Computational Biology,
    Niagara Falls, Canada, pp. pp. 1-6, 2015.
    document

33. Considering Crosstalk Effects in Statistical Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    IEEE Tr. Computer-Aided Design of Integrated Circuits and Systems,
    Volume 33, Issue 2, pp. 318-322, February 2014. DOI: 10.1109/TCAD.2013.2279515
    document

34. Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver
    Qin Tang; J. Rodriguez; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    IEEE Tr. Computer-Aided Design of Integrated Circuits and Systems,
    Volume 33, Issue 2, pp. 210-223, February 2014. DOI: 10.1109/TCAD.2013.2287179
    document

35. A System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3D MP-SoCs
    S.S. Kumar; A. Aggarwal; R. Jagtap; A. Zjajo; R. van Leuken;
    IEEE Tr. Very Large Scale Integration (VLSI) Systems,
    Volume 22, pp. 1606-1619, 2014.

36. Dynamic Thermal Estimation Methodology for High Performance 3D MPSoC
    A. Zjajo; N.P. van der Meijs; R. van Leuken;
    IEEE Tr. Very Large Scale Integration (VLSI) Systems,
    Volume 22, pp. 1920-1933, 2014.

37. Stochastic Process Variation in Deep-Submicron CMOS
    A. Zjajo;
    Springer, Volume 48 in Springer Series in Advanced Microelectronics, 2014. DOI: 10.1007/978-94-007-7781-1

38. A 0.1 pJ Freeze Vernier time-to-digital converter in 65nm CMOS
    K. Blutman; J. Angevare; A. Zjajo; N.P. van der Meijs;
    In IEEE Int. Conf. Circuits and Systems (ISCAS),
    Melbourne, Australia, IEEE, pp. 85-88, June 2014. DOI: 10.1109/ISCAS.2014.6865071
    document

39. ESL design of customizable real-time neuron networks
    M. van Eijk; C. Galuzzi; A. Zjajo; G. Smargdos; C. Strydis; R. van Leuken;
    In IEEE Biomedical Circuits and Systems Conference,
    Lausanne, Switzerland, pp. 1-4, 2014.

40. Low Power Cascaded Folding Signal Conversion
    A. Zjajo;
    In IEEE International Conference on Signal Processing,
    Hangzhou, China, pp. 1-4, 2014.

41. Statistical power optimization of deep-dubmicron digital CMOS circuits based on structured perceptron
    A. Zjajo; N. van der Meijs; R. van Leuken;
    In IEEE International Symposium on Integrated Circuits,
    Singapore, pp. pp. 1-4, 2014.

42. A System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3D MP-SoCs
    S. Kumar; A. Aggarwal; R. Jagtap; A. Zjajo; R. van Leuken;
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
    2013. in press.
    document

43. Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Solver
    Qin Tang; J. Rodriguez; A. Zjajo; M. Berkelaar; N. van der Meijs;
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
    2013. in press.

44. Considering Crosstalk Effects in Statistical Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N. van der Meijs;
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
    2013. in press.

45. Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits
    A. Zjajo; N.P. van der Meijs; R. van Leuken;
    Journal of Low Power Electronics,
    Volume 9, Issue 4, pp. 403-413, December 2013.
    document

46. Dynamic Thermal Estimation Methodology for High Performance 3D MPSoC
    A. Zjajo; N.P. van der Meijs; R. van Leuken;
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
    2013. DOI: 10.1109/TVLSI.2013.2280667
    document

47. Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms
    A. Zjajo;
    Springer-Verlag, New York, NY, USA, in Advanced Microelectronics 48, 2013. ISBN 978-94-007-7780-4.
    document

48. A Low Noise Self-Cascode Configuration OTA for Bandgap Reference Voltage Circuit
    L. Koushaeian; B. Ghafari; R. Evans; A. Zjajo;
    In 4G Wireless Communication Networks: Design, Planning and Application,
    River Publishers, 2013.
    document

49. A CMOS 0.23pJ Freeze Vernier Time-to-Digital Converter
    J. Angevare; K. Blutman; A. Zjajo; N.P. van der Meijs;
    In IEEE Nordic Microelectronics Conference,
    Vilnius, Lithuania, 2013. 4 pages.
    document

50. Interconnect and Thermal Aware 3D Design Space Exploration
    S. Kumar; A. Aggarwal; R. Jagtap; A. Zjajo; R. van Leuken;
    In ICT.OPEN,
    Eindhoven, The Netherlands, 2013.
    document

51. A 1.2V 84dB 8mW Time-Interleaved Sample and Hold Circuit in 90nm CMOS
    A. Zjajo;
    In IEEE International Conference on Electronic Devices and Solid-State Circuits,
    Hong Kong, pp. 1-2, 2013.
    document

52. Balanced Stochastic Truncation of Coupled 3D Interconnect
    A. Zjajo; N. van der Meijs; R. van Leuken;
    In IEEE International Conference on IC Design and Technology,
    Pavia, Italy, pp. 13-16, 2013.
    document

53. Signal Generation Method and Apparatus and Test Method and System Using the Same
    A. Zjajo;
    US patent number US8497792, July 2013.
    document

54. Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS
    A. Zjajo; M.J. Barragan; J. Pineda de Gyvez;
    IEEE Transactions on Instrumentation and Measurement,
    Volume 61, Issue 8, pp. 2212-2221, August 2012.
    document

55. Digital Adaptive Calibration of Multi-Step Analog to Digital Converters
    A. Zjajo; M.J. Barragan; J. Pineda de Gyvez;
    Journal of Low Power Electronics,
    Volume 8, Issue 2, pp. 182-196, April 2012.
    document

56. ADC Multi-Site Test Based on a Pre-Test with Digital Input Stimulus
    Xiaoqin Sheng; H. Kerkhoff; A. Zjajo; G. Gronthoud;
    Journal of Electronic Testing: Theory and Application,
    Volume 28, Issue 4, pp. 393-404, August 2012.
    document

57. Stimulus generation for RF MEMS switches test application
    Mingxin Song; Jinghua Yin; Zuobao Cao; Tong Wu; Yu Zhao; Zhao Jin; A. Zjajo;
    International Journal of Simulation and Process Modeling,
    Volume 7, Issue 1, pp. 107-114, February 2012.
    document

58. Direct Statistical Simulation of Timing Properties in Sequential Circuits
    J. Rodriguez; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In Proceedings of PATMOS 2012,
    Newcastle upon Tyne, UK, September 2012.
    document

59. Towards An Intrinsically Statistical SPICE-Level Simulator
    M. Berkelaar; Qin Tang; A. Zjajo; J. Rodriguez; N.P. van der Meijs;
    In Proceedings of VARI 2012,
    Sophia Antipolis, France, June 2012.
    document

60. New Statistical Timing Analysis Method Considering Process Variations and Crosstalk
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van de Meijs;
    In Proceedings of VAMM 2012,
    Dresden, Germany, March 2012.
    document

61. Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van de Meijs;
    In Proceedings of DATE 2012,
    Dresden, Germany, March 2012.
    document

62. Crosstalk-Aware Statistical Interconnect Delay Calculation
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In Proceedings of ASPDAC 2012,
    Sydney, Australia, January 2012.
    document

63. A 11 uW 0C-160C Temperature Sensor in 90 nm CMOS for Adaptive Thermal Monitoring of VLSI Circuits
    A. Zjajo; N.P. van der Meijs; T.G.R.M. van Leuken;
    In Proceedings of ISCAS 2012,
    Seoul, Korea, May 2012.
    document

64. Thermal Analysis of 3D Integrated Circuits Based on Discontinous Galerkin Finite Element Method
    A. Zjajo; N.P. van der Meijs; T.G.R.M. van Leuken;
    In Proceedings of ISQED 2012,
    Santa Clara, CA, USA, March 2012.
    document

65. Temperature Constrained Power Management Scheme for 3D MPSoC
    A. Aggarwal; S. Kumar; A. Zjajo; T.G.R.M. van Leuken;
    In Proceedings of SPI 2012,
    Sorrento, Italy, May 2012.
    document

66. Analog Circuit Testing and Test Pattern Generation
    A. Zjajo; J. Pineda de Gyvez; G. Gronthoud;
    Patent No. US 8,122,423 B2, February 2012.
    document

67. IC Testing Methods and Apparatus
    A. Zjajo; M.J. Barragan; J. Pineda de Gyvez;
    Patent No. US 8,310,265 B2, November 2012.
    document

68. Stochastic Analysis of Deep-Submicron CMOS Process for Reliable Circuits Designs
    A. Zjajo; Qin Tang; J. Pineda de Gyvez; M. Berkelaar; A. Di Bucchianico; N.P. van der Meijs;
    IEEE Transactions on Circuits and Systems-I: Regular Papers,
    Volume 58, Issue 1, pp. 164-175, January 2011.
    document

69. Pseudo Circuit Model for Representing Uncertainty in Waveforms
    A. Nigam; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In Design, Automation and Test in Europe (DATE),
    Grenoble, France, March 2011.
    document

70. Voltage Sensitivity Calculation for ViVo-based Gate Models Considering Process Variations
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van de Meijs;
    In ICT.OPEN,
    Veldhoven, the Netherlands, November 2011.
    document

71. A 1.2V 55mW 12bits Self-calibrated Dual-Residue Analog to Digital Converter in 90 nm CMOS
    A. Zjajo; J. Pineda de Gyvez;
    In International Symposium on Low Power Electronics and Design (ISLPED),
    Fukuoka, Japan, pp. 187-192, August 2011.
    document

72. A Low-Power Low-Voltage High-Performance Fully Differential OTA in 65-nm CMOS Process
    Mingxin Song; Jinghua Yin; Yijiang Cao; Zhao Jin; A. Zjajo;
    In 6th International ICST Conference on Communications and Networking in China (CHINACOM),
    Harbin, China, August 2011.
    document

73. Accuracy Consideration of a Non-Gaussian Interconnect Delay Model for Submicron CMOS Statistical Static Timing Analysis
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In IEEE International NanoElectronics Conference (INEC),
    Chang Gung University, Tao-Yuan, Taiwan, June 2011.
    document

74. Balanced Truncation of a Stable Non-Minimal Deep-Submicron CMOS Interconnect
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In International Conference on IC Design and Technology (ICICDT),
    Kaohsiung, Taiwan, May 2011.
    document

75. Statistical Delay Calculation with Multiple Input Simultaneous Switching
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In International Conference on IC Design and Technology (ICICDT),
    Kaohsiung, Taiwan, May 2011.
    document

76. Adaptive Numerical Integration Methods for Deterministic Analysis of Non-Stationary Noise in Dynamic Integrated Circuits
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In Design and Technology of Integrated Systems (DTIS),
    Athens, Greece, April 2011.
    document

77. Statistical Moment Estimation of Delay and Power in Circuit Simulation
    A. Nigam; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    Journal of Low Power Electronics,
    Volume 6, Issue 4, December 2010. Invited Paper.
    document

78. Stochastic Analysis of Deep-Submicron CMOS Process for Reliable Circuits Designs
    A. Zjajo; Qin Tang; J. Pineda de Gyvez; M. Berkelaar; A. Di Bucchianico; N.P. van der Meijs;
    IEEE Transactions on Circuits and Systems-I: Regular Papers,
    2010. DOI: 10.1109/TCSI.2010.2055291
    document

79. High-Resolution A/D Converters: Design, Test and Calibration
    A. Zjajo; J. Pineda de Gyvez;
    Dordrecht: Springer, , 2010. ISBN 978-90-481-9724-8.

80. Transistor Level Waveform Evaluation for Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In European Workshop on CMOS Variability (VARI),
    Montpellier, France, May 2010. 6 pages.
    document

81. RDE-Based Transistor-Level Gate Simulation for Statistical Static Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In IEEE Design Automation Conference (DAC),
    Anaheim, California, pp. 787-792, June 2010.
    document

82. Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS),
    Grenoble, France, September 2010.
    document

83. Statistical Moment Estimation in Circuit Simulation
    A. Nigam; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In European Workshop on CMOS Variability (VARI),
    Montpellier, France, May 2010.
    document

84. A Low-Power Digitally-Programmable Variable Gain Amplifier in 65 nm CMOS
    A. Zjajo; M. Song;
    In ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED),
    Austin, Texas, pp. 105-110, August 2010.
    document

85. Noise Analysis of Non-Linear Dynamic Integrated Circuits
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In IEEE Custom Integrated Circuits Conference (CICC 2010),
    San Jose, California, September 2010.
    document

86. An Adaptive Digital Calibration of Multi-Step A/D Converters
    A. Zjajo; J. Pineda de Gyvez;
    In 10th IEEE International Conference on Signal Processing (ICSP'10),
    Beijing, China, October 2010.
    document

87. Discrete Recursive Algorithm for Estimation of Non-Stationary Noise in Deep-Submicron Integrated Circuits
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2010),
    Shanghai, China, November 2010.
    document

88. Digital Cartesian Feedback Linearization of Switched Mode Power Amplifiers
    A. Viteri; A. Zjajo; T. Hamoen; N.P. van der Meijs;
    In 17th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2010),
    Athens, Greece, December 2010.
    document

89. Digitally Programmable continuous-Time Biquad Filter in 65-nm CMOS
    A. Zjajo; M. Song;
    In IEEE International Symposium on Radio-Frequency Integration Technology,
    Singapore, IEEE, December 2009.

90. A Simplified Transistor Model for CMOS Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N. van der Meijs;
    In 20th annual workshop on circuits, systems and signal processing--ProRISC,
    Veldhoven, STW, November 2009. ISBN 978-90-73461-62-8.
    document

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