Design of analog building blocks for ultra-low-power biomedical circuits in 40nm CMOS

Most biomedical ASICS are designed currently in reasonably old technologies. The main driver is usually cost. Recently however, the complexity of biomedical ASICs has increased, especially by addition of more and more digital processing on-chip. While traditional analog building blocks for biomedical applications don't benefit too much from technology scaling, this obviously isn't the case for digital signal processing. Hence significant research interests exists in building analog building blocks for biomedical applications in scaled technologies. Whereas older technologies allow for reasonably large chip areas because they are comparatively cheap, and allow for larger supply voltages, these assumptions no longer hold true for design in scaled technologies. Hence designing high-performance, low-power, ultra-low-noise, cost-efficient analog building blocks for biomedical applications in scaled technologies remains a technically challenging task.

During this master thesis project, the student will learn about designing in scaled technologies in general and will learn about analog design techniques for biomedical applications in general. Ideally the student can focus on design of instrumentation techniques and adapt this to different biomedical applications such as fNIRS measurements and biopotential measurements.

Assignment

During the first phase of the master thesis, the student will conduct a literature research to get him up to speed on the above aspects and get an overview of the field of biomedical analog design in scaled technologies. He will identify the core challenges and shortcomings of existing implementations.

The student will then start the design phase, which will involve coming up with a novel circuit architecture and validating the concepts through simulation. Since design in scaled technologies is quite heavily influenced by layout, the student will need to learn how to bring layout dependent effects into the design flow early on by doing initial quick placement and parasitic estimation. Ideally the student will complete the full flow of literature survey, schematic entry, verification all the way up to layout and as such be able to contribute to a tapeout.

Requirements

Prerequisites: - Analog design knowledge - Basic understanding of Cadence Virtuoso schematic editor - Basic familiarity of Cadence Virtuoso Layout editor

Contact

prof.dr.ir. Wouter Serdijn

Bioelectronics Group

Department of Microelectronics

Last modified: 2018-03-10