MSc thesis project proposal


Several RISCV cores exist; We are interested in a version which can be used in an embedded SoC, part of a larger ASIC design. IP cores of interest are: the SCR1, the PULPino, and the PicoRV32.


The goal of the project is to design a complete hardware architecture, memory, core, interfaces and IO blocks which can be used in a larger mixed signed ASIC design.

Contact René van Leuken

Circuits and Systems Group

Department of Microelectronics

Last modified: 2018-07-12