Department of Microelectronics
Faculty of Electrical Engineering, Mathematics, and Computer Science

MSc Eland

PhD student
Electronic Instrumentation (EI), Department of Microelectronics

Expertise: Energy-Efficient Data Converters

Biography

Efraïm was born in Vlissingen, The Netherlands in 1992. He received his B.Sc degree in Electrical Engineering from Delft University of Technology in 2017. In May 2017, he started pursuing his M.Sc. degree in Electrical Engineering, specialised in Microelectronics. In September 2018 he started his internsip/thesis at NXP Semiconductors, after which he graduated in October 2019 with a master thesis work on energy-efficient zoom ADCs for audio applications. Efraïm is currently pursuing the Ph.D. degree at the Electronic Instrumentation Laboratory, working on energy-efficient, high-speed data converters in collaboration with NXP Semiconductors.

Publications

  1. The Zoom ADC: An Evolving Architecture
    Eland, Efraïm; Mehrotra, Shubham; Karmakar, Shoubhik; van Veldhoven, Robert; Makinwa, Kofi A. A.;
    Harpe, Pieter; Baschirotto, Andrea; Makinwa, Kofi A.A. (Ed.);
    Cham: Springer International Publishing, , pp. 179--201, 2023. DOI: 10.1007/978-3-031-28912-5_10
    Abstract: ... Zoom ADCs combine a coarse SAR ADC with a fine delta-sigma modulator ($\Delta$$\Sigma$M) to efficiently obtain high energy efficiency and high dynamic range. This makes them well suited for use in various instrumentation and audio applications. However, zoom ADCs also have drawbacks. The use of over-ranging in their fine modulators may limit SNDR, large out-of-band interferers may cause slope overload, and the quantization noise of their coarse ADC may leak into the baseband. This chapter presents an overview of recent advances in zoom ADCs that tackle these challenges while maintaining high energy efficiency. Prototypes designed in standard 0.16 $\mu$m technology achieve SNDRs over 100 dB in bandwidths ranging from 1 to 24 kHz while consuming only hundreds of $\mu$Ws.

  2. A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC
    Mehrotra, Shubham; Eland, Efraïm; Karmakar, Shoubhik; Liu, Angqi; Gönen, Burak; Bolatkale, Muhammed; Van Veldhoven, Robert; Makinwa, Kofi A.A.;
    In ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC),
    pp. 253-256, 2022. DOI: 10.1109/ESSCIRC55480.2022.9911295

  3. A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW
    E. Eland; S. Karmakar; B. Gönen; R. van Veldhoven; K. A. A. Makinwa;
    IEEE Journal of Solid-State Circuits,
    Volume 56, pp. 1207-1215, January 2021. DOI: 10.1109/JSSC.2020.3044896
    Abstract: ... This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta–sigma modulator ( ΔΣM ) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC’s quantization noise into the audio band. The prototype ADC occupies 0.27 mm 2 in a 0.16- μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW . It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB.

  4. A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW
    E. Eland; S. Karmakar; B. Gönen; R. van Veldhoven; K. A. A. Makinwa;
    IEEE Journal of Solid-State Circuits,
    Volume 56, Issue 4, pp. 1207-1215, January 2021. DOI: 10.1109/JSSC.2020.3044896
    Abstract: ... This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta–sigma modulator ( ΔΣM ) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC’s quantization noise into the audio band. The prototype ADC occupies 0.27 mm 2 in a 0.16- μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW . It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB.

  5. A 440μW, 109.8dB DR, 106.5dB SNDR Discrete-Time Zoom ADC with a 20kHz BW
    E. Eland; S. Karmakar; B. Gönen; R. van Veldhoven; K. Makinwa;
    In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
    June 2020. DOI: 10.1109/VLSICircuits18222.2020.9162856.

  6. A 440μW, 109.8dB DR, 106.5dB SNDR Discrete-Time Zoom ADC with a 20kHz BW
    Eland, Efraïm; Karmakar, Shoubhik; Gönen, Burak; van Veldhoven, Robert; Makinwa, Kofi;
    In 2020 IEEE Symposium on VLSI Circuits,
    pp. 1-2, 2020. DOI: 10.1109/VLSICircuits18222.2020.9162856

BibTeX support

Last updated: 17 Aug 2022

Efraïm Eland

MSc students