[2022] A supply-noise-immune ADPLL with wide tuning range (Silicon Integrated)

Project Description：

The ring oscillator based PLL is widely used in SoC as clock generation, thanks to the small-size and low-power features. Nowadays, the integration level of SoC goes higher and higher, more circuits building blocks share the same power supply, causing severe supply noise coupling. The ring oscillator based PLL is naturally sensitive to supply noise, while its clock purity could be vital for the system performance. For example, in digital audio applications, the clock jitter directly affects AD/DA precision and therefore the sound quality. Many techniques [1][2] have been proposed to suppress supply noise and ripple, the purpose of this projects is to further investigate this topic and propose a novel PLL architecture for digital audio applications, where requiring low-power, low-noise and wide frequency tuning range.

Your Job is to:

• Develop a supply-noise-immune ADPLL which has: 
  • Small area
  • Low jitter
  • Power consumption < 2mW
  • Output frequency: 65MHz – 98MHz
  • Input frequency: 32kHz – 12MHz
  • < -60dBc spur if 20mV peak-peak supply ripple
• Simulate and tape-out of your PLL
• Measure the performance of your PLL after tape-out.

Job Qualifications:

• Familiar with Cadence design tool
• Good knowledge of analog and mixed-signal design
• Good understanding of PLLs
• Strong communications, documentation, and presentation skills
• Highly self-motivated and enjoying solving difficult challenges
• Currently enrolled in or entering a Master's degree program in Electrical Engineering, Computer Engineering, or related fields

About the Company 

Silicon Integrated Co., Ltd is a high-tech startup company focus on high-performance mixed-signal IC design. It was founded in January 2016 in Wuhan and it has R&D centers in Europe, Shenzhen and Shanghai. Silicon Integrated has two main product lines: 3D image sensors and smart audio amplifiers. The smart audio amplifier wins over the business by excellent product differentiation, with high quality performance and competitive price. The business value is fully recognized by the tier-one smartphone manufacturers in China. 

Reference:

[1] D. Kim and S. Cho, "A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop," 2017 Symposium on VLSI Circuits, 2017, pp. C180-C181, doi: 10.23919/VLSIC.2017.8008473.

[2] Y. Chen, J. Gong, R. B. Staszewski and M. Babaie, "A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <-54-dBc Spurs Under 50-mV $_{pp}$ Supply Ripple," in IEEE Journal of Solid-State Circuits, doi: 10.1109/JSSC.2021.3123386.

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Last modified: 2022-03-11