MSc J Liao
Electronic Instrumentation (EI), Department of Microelectronics
Expertise: Power management ICs
Jieyu Liao received her B.Sc. degree in Electrical Engineering from National Sun Yat-Sen University, Taiwan, in 2007, and the M.Sc. degree in Electrical and Control Engineering from National Chiao-Tung University, Taiwan, in 2009. From 2009 to 2013, she was with Mediatek Inc., focusing on switching converter and linear regulator design for mobile devices. From 2013 to 2019, she served at Novatek Microelectronics Corp. Currently she is working as a researcher at the Electronic Instrumentation Laboratory of Delft University of Technology, The Netherlands. Her research interests include low-power energy harvester, DC/DC converter, AC/DC converter and voltage regulator.
- Suppression Approach to Main-Beam Deceptive Jamming in FDA-MIMO Radar Using Nonhomogeneous Sample Detection
Lan, Lan; Liao, Guisheng; Xu, Jingwei; Zhang, Yuhong; Fioranelli, Francesco;
Volume 6, pp. 34582-34597, 2018. DOI: 10.1109/ACCESS.2018.2850816
- A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications
C. C. Li; M. S. Yuan; C. H. Chang; Y. T. Lin; C. C. Liao; K. Hsieh; M. Chen; R. B. Staszewski;
In 2017 IEEE International Solid-State Circuits Conference (ISSCC),
pp. 332-333, Feb 2017. DOI: 10.1109/ISSCC.2017.7870396
Keywords: ...DC-DC power converters;FinFETs;Logic gates;Oscillators;Switches;Topology;Voltage control.
- A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS
Chao-Chieh Li; T. H. Tsai; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo; K. Hsieh; M. Chen; A. Ximenes; R. B. Staszewski;
In 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits),
pp. 1-2, June 2016. DOI: 10.1109/VLSIC.2016.7573551
Keywords: ...CMOS integrated circuits;MOSFET circuits;digital phase locked loops;transformers;DCO;FinFET CMOS;LC-tank-based ADPLL;capacitor banks;fractional-N all-digital PLL;frequency 10.8 GHz to 19.3 GHz;frequency reference clock;inverter-based ring-oscillator PLL;magnetic coupling transformer;metastability-resolution scheme;size 10 nm;time 725 fs;Capacitors;Clocks;FinFETs;Jitter;Phase locked loops;Q-factor;Tuning.
- 14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S
T. H. Tsai; M. S. Yuan; C. H. Chang; C. C. Liao; C. C. Li; R. B. Staszewski;
In 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers,
pp. 1-3, Feb 2015.
- A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS
Feng-Wei Kuo; R. Chen; K. Yen; Hsien-Yuan Liao; Chewn-Pu Jou; Fu-Lung Hsueh; M. Babaie; R. B. Staszewski;
In 2014 Symposium on VLSI Circuits Digest of Technical Papers,
pp. 1-2, June 2014.
Last updated: 5 Sep 2019