Agenda

PhD thesis defence Mark Stoopman

• Friday, 9 September 2016
• 12:00-15:00
• Delft, Aula, Senaatszaal

Circuit Design for Highly Sensitive RF-Powered Wireless Sensor Nodes

Emerging applications such as Internet of Things (IoT), smart buildings and warehouse inventory management are important driving forces behind the development of Wireless Sensor Nodes (WSNs). With future advancements made in the semiconductor industry, these WSNs are expected to become smaller, cheaper, more reliable and with improved functionality. The prospect of energy scavenged WSNs is to eliminate the burden of battery replacement, thereby significantly saving on maintenance costs in large WSN networks.

This dissertation focuses on the research, design and implementation of various circuit blocks and the system integration of energy scavenged WSNs used in the aforementioned applications. To select a suitable energy harvester, four different energy harvesting approaches are discussed: vibrational, thermal, photovoltaic and RF. Of these harvesters, it shows that RF-powered WSNs have the distinct advantage over WSNs using other forms of energy harvesting that they are low cost and can operate wirelessly in a large variety of applications, even in cold, dark and static environments. Moreover, additional advantages such as utilizing a dedicated RF source for both energy harvesting as well as the generation of a reference frequency greatly reduces the complexity and power consumption of the WSN.

A co-design methodology is presented to optimize the interface between the RF energy harvester and the WSN electronics for maximum sensitivity, efficiency and output power. First, general co-design principles for antennaelectronics interfaces in the receiving mode are introduced, which includes optimum reception of wireless information and wireless power. It is shown that the choice of interface impedance plays a crucial role during the optimization procedure and that, besides maximum power transfer, the interface needs to be optimized for either voltage or current, depending on which is more favorable for the electronics. Design examples are given to, for example, improve noise figure, efficiency and sensitivity without increasing power consumption.

Based on the presented co-design principles, a CMOS rectifier and a compact loop antenna are presented for a highly sensitive RF energy harvester. A 5-stage cross-connected differential rectifier with a complementary MOS diode in the last rectifying stage is designed that significantly improves the harvester?s ability to store and hold energy over a longer period of time than a conventional MOS diode. A low resistive and high-Q interface is utilized to obtain good sensitivity. To compensate variations at the interface, a control loop with a 7-bit binary-weighted capacitor bank is proposed that provides self-calibration. The chip is implemented in TSMC 90 nm CMOS technology, includes ESD protection and is directly mounted on the backside of the custom designed antenna. Measurements in an anechoic chamber at 868 MHz demonstrate an end-to-end maximum PCE of 40% and a sensitivity of -27 dBm to generate 1V across a capacitive load. In an office corridor, 1V could be generated from a 1.78 W RF source at 27 meter distance.

A high efficiency tuned switching Power Amplifier (PA) is proposed for < 0 dBm output power. It is shown theoretically that an optimum duty cycle exists for maximum drain efficiency for a given switch and effective load resistance. To set this duty cycle, an on-chip duty cycle calibration loop is proposed that fixes the duty cycle over PVT variations. A 2.4 GHz PA prototype is implemented in 40nm CMOS technology and supports On-Off Keying (OOK) modulation with pulse shaping capabilities. A global efficiency of 40% is achieved when delivering -5 dBm to a 50 W load, which compares favorably to the state-of-the-art. Due to the introduced memory in the duty cycle calibration loop, the rise and fall times are kept below 3.3 ns, making high data rate OOK modulation feasible.

The findings in this thesis have been used for the system integration of a compact RF-powered DLL-based 2.4 GHz CMOS transmitter. The received dedicated RF signal is used for both RF energy harvesting as well as frequency synthesis. An RF energy harvester with a nanowatt power management circuit harvests and subsequently monitors the energy in the storage capacitor to determine when enough energy is accumulated to initiate wireless data transmission. Once the voltage regulator and bias current circuit blocks are enabled, the incoming RF carrier is extracted and used as frequency reference. The frequency synthesizer consits of a frequency divider, Delay Locked Loop (DLL) and XOR-based frequency multiplier and thus allows for a compact integrated solution. All building blocks have been implemented in 40 nm CMOS technology and occupy only 0.16 mm2. Experimental results show a maximum rectifier efficiency of 36.83% at -11.47 dBm. In harvesting mode, the complete power management circuit only consumes 120 nA. For a 1 mF storage capacitor and -18.4 dBm minimum available power at 915 MHz RF input, the TX outputs a continuous 2.44 GHz RF signal of -2.57 dBm for 128 ms with 36.5% PA drain efficiency and 23.9% global efficiency. The complete TX consumes 1.46 mW during OOK modulation at 0.5 Mbps.

Overview of PhD Thesis Defence